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Software/Hardware Co-Verification for Custom Instruction Set Processors
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DOI：10.1109/ACCESS.2021.3131213.png)
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Abstract
En 中文
Verification of software and processor hardware usually proceeds separately, software analysis relying on the correctness of processors executing machine instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption. In this paper we present a novel formal approach for hardware/software co-verification targeting processors with custom instruction set extensions. We detail two different approaches for checking whether the hardware fulfills the requirements expected by the software analysis. The approaches are designed to explore a trade-off between generality of the verification and computational effort. Then, we describe the integration of software and hardware analyses for both techniques and describe a fully automated tool chain implementing the approaches. Finally, we demonstrate and compare the two approaches on example source code with custom instructions, using state-of-the-art software analysis and hardware verification techniques.
Keywords:
Software
Hardware
Instruction sets
Codes
Tools
Runtime
Semantics
Software analysis
abstract interpretation
custom instruction
hardware verification
Journal
IF:
3.6
Papers:
9.8W
Citations:
29.4W
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