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Spatial-Temporal Hybrid Neural Network With Computing-in-Memory Architecture

delete2021-07-01
delete17
PRE
AI
K
Kangjun Bai *
L
Lingjia Liu
Y
Yang Yi
DOI：10.1109/TCSI.2021.3071956delete
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Abstract

Abstract

En 中文
Deep learning (DL) has gained unprecedented success in many real-world applications. However, DL poses difficulties for efficient hardware implementation due to the needs of a complex gradient-based learning algorithm and the required high memory bandwidth for synaptic weight storage, especially in today's data-intensive environment. Computing-in-memory (CIM) strategies have emerged as an alternative for realizing energy-efficient neuromorphic applications in silicon, reducing resources and energy required for neural computations. In this work, we exploit a CIM-based spatial-temporal hybrid neural network (STHNN) with a unique learning algorithm. To be specific, we integrate both multilayer perceptron and recurrent-based delay-dynamical system, making the network becomes linear separable while processing information in both spatial and temporal domains, better yet, reducing the memory bandwidth and hardware overhead through the CIM architecture. The prototype fabricated in 1841nm CMOS process is built of fully-analog components, yielding an average on-chip classification accuracy up to 86.9% on handprinted alphabet characters with a power consumption of 33mW. Beyond that, through the handwritten digit database and the radio frequency fingerprinting dataset, software-based numerical evaluations offer 1.6-to-9.8x and 1.9-to-4.4x speedup, respectively, without significantly degrading its classification accuracy compared to the cutting-edge DL approaches.
Keywords:
Deep learning
computing-in-memory
spatial-temporal architecture
analog computing
delay-dynamical system
hybrid neural network
on-chip classification
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Journal

IEEE Transactions on Circuits and Systems I-Regular Papers cover
IEEE Transactions on Circuits and Systems I-Regular Papers
IF:
5.2
Papers:
9.7K
Citations:
2.2W

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