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Spintronic Content Addressable Memory With Integrated Boolean Logic and Arithmetic Functions
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DOI：10.1109/ACCESS.2025.3551411.png)
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Abstract
En 中文
To address growing data processing demands, traditional von Neumann architectures face increased power consumption and delay issues. In response, this paper presents a novel latch-based hybrid CMOS/MTJ content-addressable memory (TCAM) designed to perform Boolean logic, as well as full adder (FA) and full subtractor (FS) operations, within a computing-in-memory (CIM) architecture. The proposed cell efficiently compares 4-bit encoded data in TCAM mode while supporting 8-bit data processing in computing mode, improving area efficiency. Additionally, the reduced number of active paths between the power supply and ground during the read phase significantly lowers power consumption. Complemented by peripheral circuits, a scalable array architecture has been developed to demonstrate the system's feasibility. Post-layout simulations using 40 nm technology in Cadence Virtuoso and HSPICE show that the proposed design reduces power consumption and PDP by up to 35% in TCAM mode and up to 65% in COMPUTING mode compared to previous solutions. Furthermore, Monte Carlo simulations confirm the design's robust resilience to process variations, highlighting its potential for reliable, energy-efficient operation. Also, the suggested design in the presence of temperature variations is investigated, and PDP results for temperatures range 0 degrees C to 100 degrees C show design resilience. In addition, our results indicate that the proposed strategy significantly reduces power consumption in neural network applications compared to its counterparts.
Keywords:
Computer architecture
Circuits
Microprocessors
Logic
Magnetic tunneling
Logic gates
Transistors
Power demand
FinFETs
CMOS technology
Content addressable memory (CAM)
Boolean logic
full adder (FA) and full subtractor (FS)
computing in memory (CIM)
process variation
Journal
IF:
3.6
Papers:
9.8W
Citations:
29.4W