.png){kind=icon}
.png){kind=icon}
Return
Spintronic Threshold Logic Array (STLA) A compact, low leakage, non-volatile gate array architecture
.png){kind=icon}
PRE
AI
DOI：10.1016/j.jpdc.2013.09.013.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
This paper describes a novel, first of its kind architecture for a threshold logic gate using conventional MOSFETs and an SIT-MTJ (Spin Transfer Torque-Magnetic Tunneling Junction) device. The resulting cell, called STL which is extremely compact can be programmed to realize a large number of threshold functions, many of which would require a multilevel network of conventional CMOS logic gates. Next, we describe a novel array architecture consisting of STL cells onto which complex logic networks can be mapped. The resulting array, called STLA has several advantages not available with conventional logic. This type of logic (1) is non-volatile, (2) is structurally regular and operates like DRAM, (3) is fully observable and controllable, (4) has zero standby power. These advantages are demonstrated and compared by implementing a 16-bit carry look-ahead adder and a 32-bit Wallace tree multiplier in STLA and FPGA. (C) 2013 Elsevier Inc. All rights reserved.
Keywords:
Threshold logic
Spin Transfer Torque-Magnetic Tunneling Junction (STT-MTJ)
Gate array architecture
Low leakage magnetic circuits
Journal
IF:
4
Papers:
3.8K
Citations:
4.8K