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Stochastic sampling via synaptic delay in spiking RBMs using integrated resistive and threshold switching devices
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DOI：10.1039/D6NH00158K.png)
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Abstract
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Spiking neural networks (SNNs) have emerged as promising low-power architectures for next-generation neuromorphic hardware because spike-based operation naturally supports spatiotemporal information processing. Among SNN models; spiking restricted Boltzmann machines (spiking RBMs) enable sampling-based learning and inference; but stable operation requires sufficient stochasticity at the neuron and synapse levels. Under temporally uniform input spike trains; such as sensor-driven inputs; limited intrinsic randomness can degrade learning performance. Here; a delay-based hardware strategy is presented in which synaptic propagation delay serves as a source of stochasticity for sampling in spiking RBMs. The corresponding synaptic unit cell consists of a synapse for weight storage and a delay module for temporal stochasticity. The delay module; based on serially integrated resistive random-access memory (RRAM) and threshold-switching (TS) devices; enables tuning of the TS turn-on delay through the RRAM resistance. Higher resistance increases the mean delay; and the measured delays follow a log-normal distribution. Compact modeling and circuit-level simulation confirm compatibility of the delay behavior with CMOS neuron-synapse circuits. Application of delay distributions to MNIST learning in spiking RBMs yields higher accuracy than both a no-delay baseline and conventional stochastic implementations based on random number generators. The RRAM–TS-based synaptic delay circuit therefore offers an efficient hardware primitive for introducing stochasticity into neuromorphic systems without complex and power-consuming additional peripherals.
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