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Sum Propagate Adders
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DOI：10.1109/TETC.2021.3068729.png)
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Abstract
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Binary adders are present in every digital computer system. Even if their structure has evolved significantly over the last decades following the progress in logic and circuit design, the scaling of implementation technologies, and the improvement of logic synthesis tools, the fundamental carry-propagation algorithm that guides their operation remains unchanged. This work takes a different path and explores the possibility of performing addition by propagating directly the sum bits of previous bit positions instead of carries. The transformation of binary carry-propagate addition to an equivalent sum propagate addition opens up a whole new design space that spans from ripple-sum to sum-lookahead adders. New parallel-prefix structures that follow the sum-propagation paradigm are presented using a newly introduced associative prefix operator. Sum-propagate and carry-propagate adders have asymptotically the same area and delay complexity. In practice, however, carry propagate adders exhibit better characteristics when implemented in currently established implementation technologies. This gap is expected to reduce in the future using multiple-independent-gate transistors that are promising functionality-enhanced beyond CMOS device technologies, and allow the cost-efficient implementation of AND-XOR operations involved in sum-propagate adders.
Keywords:
Adders
Field programmable gate arrays
Delays
Logic gates
Transistors
CMOS technology
Wiring
Binary addition
parallel prefix adders
FPGA adders
computer arithmetic
logic design
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