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Symmetry in temporal logic model checking

delete2006-09-30
delete62
PRE
AI
A
Alice Miller *
A
Alastair F. Donaldson
M
Muffy Calder
DOI：10.1145/1132960.1132962delete
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Abstract

Abstract

En 中文
Temporal logic model checking involves checking the state-space of a model of a system to determine whether errors can occur in the system. Often this involves checking symmetrically equivalent areas of the state-space. The use of symmetry reduction to increase the efficiency of model checking has inspired a wealth of activity in the area of model checking research. We provide a survey of the associated literature.
Keywords:
theory
verification
model checking
symmetry
quotient graph
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ACM Computing Surveys cover
ACM Computing Surveys
IF:
28
Papers:
2.4K
Citations:
3.5W

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