Synapse Compression for Event-Based Convolutional-Neural-Network Accelerators

doi:10.1109/TPDS.2023.3239517

Synapse Compression for Event-Based Convolutional-Neural-Network Accelerators

2023-04-01

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DOI：10.1109/TPDS.2023.3239517

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Manufacturing-viable neuromorphic chips require novel compute architectures to achieve the massively parallel and efficient information processing the brain supports so effortlessly. The most promising architectures for that are spiking/event-based, which enables massive parallelism at low complexity. However, the large memory requirements for synaptic connectivity are a showstopper for the execution of modern convolutional neural networks (CNNs) on massively parallel, event-based architectures. The present work overcomes this roadblock by contributing a lightweight hardware scheme to compress the synaptic memory requirements by several thousand times-enabling the execution of complex CNNs on a single chip of small form factor. A silicon implementation in a 12-nm technology shows that the technique achieves a total memory-footprint reduction of up to 374x compared to the best previously published technique at a negligible area overhead.

Keywords:

CNN

compression

dataflow

event-based

hardware accelerator

near-memory compute

neuromorphic

sparsity

spiking

Synapse Compression for Event-Based Convolutional-Neural-Network Accelerators

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