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T2Tree: A Deterministic Algorithmic Framework for High-Speed Packet Classification
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DOI：10.1109/TNSE.2026.3676491.png)
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Abstract
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Packet classification in high-speed networks requires hardware acceleration for line-rate processing, yet existing decision tree algorithms struggle to effectively harness hardware parallelism. This paper presents T2Tree, a hardware-centric algorithm that strategically distributes wildcard-heavy rules across tree nodes to maximize parallel processing. T2Tree’s key innovation lies in its hardware-aware rule distribution: by embedding wildcard-heavy rules throughout the hierarchy, it enables concurrent matching during traversal, potentially hiding latency within pipeline stages and achieving minimal overhead. The elimination of rule replication while maintaining full coverage allows T2Tree to dramatically reduce the number of decision trees required, making complete rule set implementation feasible within constrained on-chip resources. The algorithm features a unified framework that adapts to diverse rule sets without reconfiguration, a critical advantage for programmable hardware. Experimental results demonstrate significant improvements in throughput and memory efficiency compared to state-of-the-art approaches, while maintaining robust update performance. This hardware-software co-design is particularly suitable for FPGA-based accelerators and packet processing engines where deterministic latency, resource efficiency, and predictable memory usage are paramount.
Keywords:
Packet classification
decision tree
hardware specific
FPGA
SDN
Journal
I
IF:
7.9
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2.5K
Citations:
10.0K