.png){kind=icon}
.png){kind=icon}
Return
Ternary multiplexer and encoder implementations using reconfigurable logic-in-memory cells
.png){kind=icon}
OA
AI
DOI：10.1016/j.asej.2026.104309.png)
.png){kind=icon}
.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
The ternary numeral system is recognized for its superior information density and circuit efficiency relative to conventional binary systems. When integrated with logic-in-memory (LiM) architectures, this approach significantly reduces interconnect complexity and power consumption, enabling compact and efficient computational frameworks. This study proposes a ternary LiM (T-LiM) cell comprising triple-gated feedback field-effect transistors (TG FBFETs). By dynamically reconfiguring the constituent TG FBFETs, the proposed T-LiM cell successfully executes ternary multiplexer, 3-to-1 encoder, and 9-to-2 encoder operations, achieving low power consumption of 4.75, 8.62, and 17.15 nW, respectively. Compared with previously reported ternary logic circuits, the proposed T-LiM cell reduces the power consumption of the 3-to-1 encoder and 9-to-2 encoder operations by approximately 95.5% and 99.0%, respectively. Moreover, the T-LiM cell retains output states for 10 ms under zero-bias conditions, effectively demonstrating integrated logic and memory functionalities.
Keywords:
Logic-in-memory cells
Reconfigurable logic
Triple-gated field-effect transistors
Ternary multiplexer
Ternary encoder
AI Summary
Key information extracted from the uploaded paper, including a brief overview, abstract, background, key highlights, visual analysis, and future outlook.