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TestLock: a testability logic locking method against machine learning-based oracle-less attacks

delete2025-09-09
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PRE
AI
M
Marziye Pandi
M
Mostafa Moghaddas
H
Hakem Beitollahi *
DOI:10.1007/s11227-025-07803-9delete
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Abstract

Abstract

En 中文
Logic Locking (LL) is a crucial technique for safeguarding intellectual property (IP) within the semiconductor supply chain. However, the emergence of sophisticated machine learning-based attacks has posed significant challenges to the security of LL designs. This paper introduces TestLock, a novel LL method that leverages circuit testability metrics to enhance resistance against these advanced threats. By strategically selecting node pairs based on their controllability and observability, TestLock significantly obfuscates the circuit’s internal structure, making it considerably more difficult for attackers to identify and exploit vulnerabilities. The proposed method is lightweight in computation, while introducing only modest hardware overhead, making it applicable to a wide range of hardware designs. Furthermore, due to the systematic nature of SCOAP-guided node selection and the scalability of the approach, TestLock can be effectively integrated into large-scale systems. As modern security-critical applications increasingly rely on high-throughput and real-time performance, TestLock offers a logic-level defense mechanism that aligns with the requirements of secure implementations. Additionally, evaluation against state-of-the-art attacks, including MuxLink and SCOPE, demonstrates that TestLock’s superior performance in preserving IP integrity. Our results indicate a substantial reduction in attack accuracy, with a 57.13% decrease observed for MuxLink and a 24.22% reduction for SCOPE. TestLock offers a robust and effective defense against these attacks, safeguarding IP from unauthorized access and reverse engineering.
Keywords:
Hardware security
Logic locking
IP protection
Machine learning
SCOAP testability measures

Journal

T
The Journal of Supercomputing
IF:
0
Papers:
647
Citations:
0

Organization

D
Department of Computer Science
Scholars:
1.7K
Papers: 998
Citations: 8
Cited Papers

Cited Papers

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On Improving the Security of Logic Locking
err2016-09-01
err0
PREAI
errMuhammad Yasin; Jeyavijayan JV Rajendran; Ozgur Sinanoglu; Ramesh Karri
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Logic locking for IP security: A comprehensive analysis on challenges, techniques, and trends
err2023-06-01
err7
PREAI
errGandhi, Jugal; Shekhawat, Diksha; Santosh, M.; Pandey, Jai Gopal
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Removal Attacks on Logic Locking and Camouflaging Techniques
err2020-04-01
err142
errOAAI
errYasin, Muhammad; Mazumdar, Bodhisatwa; Sinanoglu, Ozgur; Rajendran, Jeyavijayan
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A Primer on Hardware Security: Models, Methods, and Metrics
err2014-08-01
err506
PREAI
errRostami, Masoud; Koushanfar, Farinaz; Karri, Ramesh
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Fault Analysis-Based Logic Encryption
err2015-02-01
err368
PREAI
errRajendran, Jeyavijayan; Zhang, Huan; Zhang, Chi; Rose, Garrett S.; Pino, Youngok; Sinanoglu, Ozgur; Karri, Ramesh
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