The irregular Z-buffer: Hardware acceleration for irregular data structures

Johnson, GS

doi:10.1145/1095878.1095889

The irregular Z-buffer: Hardware acceleration for irregular data structures

2005-10-01

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DOI：10.1145/1095878.1095889

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The classical Z-buffer visibility algorithm samples a scene at regularly spaced points on an image plane. Previously, we introduced an extension of this algorithm called the irregular Z-buffer that permits sampling of the scene from arbitrary points on the image plane. These sample points are stored in a two-dimensional spatial data structure. Here we present a set of architectural enhancements to the classical Z-buffer acceleration hardware which supports efficient execution of the irregular Z-buffer. These enhancements enable efficient parallel construction and query of certain irregular data structures, including the grid of linked lists used by our algorithm. The enhancements include flexible atomic read-modify-write units located near the memory controller, an internal routing network between these units and the fragment processors, and a MIMD fragment processor design. We simulate the performance of this new architecture and demonstrate that it can be used to render high-quality shadows in geometrically complex scenes at interactive frame rates. We also discuss other uses of the irregular Z-buffer algorithm and the implications of our architectural changes in the design of chip-multiprocessors.

Keywords:

algorithms

design

performance

real-time graphics hardware

shadow algorithms

visible surface algorithms

architecture

computer graphics

The irregular Z-buffer: Hardware acceleration for irregular data structures

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