.png){kind=icon}
.png){kind=icon}
Return
Thermal aware modern VLSI floorplanning using Chiplet multi-objective optimization based Sequential Pair
.png){kind=icon}
PRE
AI
DOI：10.1080/02533839.2026.2666170.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
Creating integrated circuits (ICs) that are three-dimensional (3D) is a major issue for heat control. Modern electronic equipment must be designed with efficient heat management in mind. To maximize the thermal performance of 3D ICs, partial differential equations are frequently employed in several costly simulations. To solve this problem, neural network-based prediction models have been developed. Nevertheless, the current research either exclusively addresses two-dimensional temperature fields or is unable to handle novel designs with unforeseen configurations, such as different locations for heat sources and boundary conditions. This paper presents a novel floor-planning method that reduces the maximum temperature while accounting for thermal variables using a Chiplet Multi-Objective Optimization (CMO) strategy. The proposed approach evaluates floor planning using Sequential Pairs and a CMO algorithm, which was utilized to manage high temperatures based on energy usage while an algorithm was employed to eliminate dead space areas. The recommended method is demonstrated using benchmark circuits from the Microelectronics Center of North Carolina (MCNC). This article illustrates the accuracy and efficiency of the algorithm using the multi-window display system. The optimal solution can lower the system temperature by 8.34 K and the communication consumption by 232.13 mu J, according to the proposed technique.
Keywords:
Chiplet multi-objective optimization
floorplanning
MCNC benchmark circuits
Journal
J
IF:
1.2
Papers:
151
Citations:
1.1K