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Three-dimensional integrated hybrid complementary circuits for large-area electronics
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DOI：10.1038/s41928-025-01469-0.png)
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Abstract
En 中文
The development of low-power computing sectors requires compact, power-efficient and high-performance integrated circuits. Hybrid technology that combines n-type metal oxide thin-film transistors and p-type organic thin-film transistors offers a potential solution. However, increasing the transistor density of these systems through vertical stacking is challenging due to issues related to thermal budget and interface roughness. Here we report a six-stack hybrid complementary transistor technology that has 41 layers and uses n-type indium oxide (In2O3) and a p-type organic semiconductor (C16IDT-BT) as channel materials. We test 600 transistors and show that n-type oxide devices and p-type organic devices exhibit comparable field-effect mobilities and saturation currents. We also create 300 hybrid inverters by integrating the oxide and organic transistors; the circuits exhibit a gain of 94.84 V V−1 and a power consumption of 0.47 µW. We also fabricate NAND and NOR gates comprising transistors from four stacks. Thermal stability analysis shows that device characteristics begin to degrade above 50 °C, a known limitation of low-thermal-budget processes. Such performance is sufficient for many large-area electronics applications, but further thermal optimization will be necessary to extend operational robustness towards standard industrial conditions. A six-stack hybrid complementary transistor technology that uses n-type indium oxide and a p-type organic semiconductor as channel materials can be used to build inverters that exhibit a gain of 94.84 V V−1 and a power consumption of 0.47 µW.
Keywords:
hybrid complementary transistors
three-dimensional integration
low-power electronics
indium oxide
organic semiconductor
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