.png){kind=icon}
.png){kind=icon}
Return
Timing-Driven Obstacle-Avoiding X-Architecture Steiner Minimum Tree Algorithm With Slack Constraints
.png){kind=icon}
PRE
AI
DOI：10.1109/TSMC.2024.3353534.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
SMT is an optimized model for solving the routing problem of a multipin net in very large-scale integrated circuits. As the appearance of various obstacles on chips, the obstacle-avoiding problem has attracted much attention in recent years. Meanwhile, since interconnect delay plays a major role in chip delay, timing analysis is another critical problem worthy of consideration when constructing an Steiner minimum tree (SMT). Furthermore, the introduction of the X-architecture allows for better utilization of routing resources. In this article, a timing-driven obstacle-avoiding X-architecture Steiner minimum tree algorithm with slack constraints (TD-OAXSMT-SC) is proposed to consider obstacle-avoiding, timing slack constraints, and X-architecture simultaneously for the first time. The TD-OAXSMT-SC algorithm consists of four major stages: 1) in the routing tree initialization stage, this article constructs an X-architecture Prim-Dijkstra spanning tree as the initial routing tree with minimum total delay; 2) in the particle swarm optimization (PSO)-based routing tree iteration stage, a novel discrete PSO algorithm based on genetic operators is proposed to obtain a high-quality routing tree; 3) in the routing tree standardization stage, two effective standardization strategies are proposed to obtain a routing tree that satisfies both obstacle-avoiding and timing slack constraints; and 4) in the routing tree optimization stage, the connection of interconnected wires is optimized in a global manner, thus obtaining an optimized routing tree. Experimental results show that the proposed TD-OAXSMT-SC algorithm outperforms the state-of-the-art methods in routing quality with slack constraints.
Keywords:
Routing
Delays
Integrated circuit interconnections
Very large scale integration
Optimization
Wires
Pins
Obstacle-avoiding
PSO
SMT
timing-driven routing
timing slack constraints
X-architecture routing
Journal
IF:
10.5
Papers:
1.1W
Citations:
5.0W