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Toward an Efficient Multiview Display Processing Architecture for 3DTV
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DOI：10.1109/TCSII.2016.2595591.png)
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Abstract
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In this brief, we present an efficient architecture for multiview 3-D television (3DTV) processing. The architecture, which is designed for 4/8/9/16-compatible multiview 1080p and 4K displays, includes a frame memory controller, a parallel video scaling engine, and a subpixel rearrangement module for slanted lenticular displays. First, we observe and leverage computation locality in the viewpoint scaling problem, significantly reducing area and power overheads. Next, we propose an approximate formulation of the subpixel rearrangement computation, trading substantial computation energy for a small and analytically bounded error. Finally, we design a distributed data placement scheme that takes advantage of the inherent structured parallelism to amortize the cost of DRAM precharge cycles. Our proof-of-concept field-programmable gate array (FPGA) implementation is capable of processing frame-compatible streams in 1080p at 60 Hz and 4K at 30 Hz. Overall, the proposed optimizations lower the area by 2.75x for our FPGA implementation, and both area and power by 3.5x for an ASIC implementation.
Keywords:
Frame-compatible format
4K/8K multiview 3DTV
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