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Transition-Region Co-Optimization for Enhanced <italic>dV/dt</italic> Ruggedness in 4H-SiC MOSFETs
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DOI：10.1109/tpel.2026.3696697.png)
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Abstract
En 中文
Under high-speed switching conditions, silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) are susceptible to reliability failures induced by high <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dV/dt</i> stress, which has emerged as a critical bottleneck limiting their high-frequency and high-efficiency applications. This article presents a systematic investigation of the failure behavior and underlying physical mechanisms of 1200 V 4H-SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small>s under high <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dV/dt</i> conditions. Transient electric-field concentration across the thin gate oxide in the transition region is identified as the primary trigger of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dV/dt</i>-induced failure, based on double-pulse testing combined with thermal emission microscope, focused ion beam, and scanning electron microscopy failure analyzes. Further technology computer aided design (TCAD) transient simulations reveal that both an excessive thin-gate-oxide length and dynamic incomplete-ionization effects contribute to severe transient gate-oxide electric-field intensification during fast voltage ramping. Based on these insights, a co-optimization strategy centered on electric-field redistribution is proposed and experimentally validated by shortening the thin-gate-oxide length and reducing the surface doping concentration in the transition region. The optimized device can operate reliably at <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dV/dt</i> exceeding 330 V/ns, with no failure observed even under the extreme condition of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol {R}_{\boldsymbol {g}}$</tex-math></inline-formula> = 0 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol {\Omega }$</tex-math></inline-formula>, representing more than a threefold improvement over the original device. Furthermore, continuous-pulse stress tests demonstrate stable gate leakage current after 2.5 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> high-speed switching cycles under <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dV/dt</i> stress above 300 V/ns, indicating no observable gate-oxide degradation. Large-scale statistical measurements on 1200 V devices confirm that key static parameters, including threshold voltage, on-resistance, and breakdown voltage, remain unchanged, while high-temperature reverse-bias testing at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${\text{175}}\; ^{\circ }{\text{C}}$</tex-math></inline-formula> for 1000 h verifies that the proposed optimization does not compromise long-term static reliability.
Keywords:
Dynamic incomplete ionization
electric-field concentration
high dv/dt robustness
silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs)
transition-region
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