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Unified and Efficient Factor Graph Accelerator Design for Robotic Optimization
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AI
DOI：10.1145/3771846.png)
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Abstract
En 中文
Despite extensive efforts, existing approaches to design accelerators for optimization-based robotic applications have limitations related to insufficient real-time performance and high energy consumption. Some methods focus on designing general-purpose matrix computation units, but fail to consider specific characteristics of robotic algorithms. Other methods aim at designing dedicated accelerators that achieve excellent performance but suffer from limited flexibility. To balance between general-purpose and specialized designs, this article proposes a hardware accelerator that, through a unified pose representation and factor graph abstraction, can solve nonlinear optimization algorithms for localization, planning, and control on the same piece of circuits. Through carefully designed pipeline, circuit structure optimization, fixed-point arithmetic, and sparse data compression, the accelerator design achieves high performance and high energy efficiency. The experimental results on FPGA demonstrate that compared to state-of-the-art acceleration solutions, our design achieves up to 107.9x speedup, 7.2x energy reduction, while achieving similar accuracy.
Keywords:
Robotic computing
factor graph
optimization
FPGA
Journal
A
IF:
1.8
Papers:
96
Citations:
1.1K