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Using model-checking for Timed Automata to parameterize logic control programs

delete1998-03-01
delete1
PRE
AI
S
Stefan Kowalewski *
S
Sebastian Engell
R
Ralf Huuck
Y
Yassine Lakhnech
B
Ben Lukoschus
L
Luis Urbina
DOI：10.1016/S0098-1354(98)00170-7delete
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Abstract

Abstract

En 中文
In this contribution we describe how the modeling and analysis framework of Timed Automata can be used to determine valid parameter ranges for timers in logic control programs. The procedure is illustrated by means of a simple process engineering example for which the complete Timed Automata model is presented. To analyse the model, the tool HyTech is used which provides routines to determine values of model parameters depending on. reachability conditions. (C) 1998 Elsevier Science Ltd. All rights reserved.
Keywords:
Programmable Logic-Controllers
process safety
validation
Timed Automata
HyTech
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Journal

C
Computers and Chemical Engineering
IF:
3.9
Papers:
8.1K
Citations:
1.7W

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