VAR-DRAM: Variation-aware framework for efficient dynamic random access memory design

doi:10.1016/j.suscom.2026.101391

VAR-DRAM: Variation-aware framework for efficient dynamic random access memory design

2026-05-20

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DOI：10.1016/j.suscom.2026.101391

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• The paper presents an efficient power management technique for the bank granularity for modern-day DRAM devices. • We identify process variation affected regions of the DRAM device, which are slower in terms of access latency, and, use the aforementioned power management technique to save power from these regions while maintaining the performance of the DRAM device.

Keywords:

DRAM power management

process variation

access latency

bank granularity

power-efficient design

VAR-DRAM: Variation-aware framework for efficient dynamic random access memory design

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