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VASE: Vector Memory Using Bit-Level Address Segmentation for High-Speed Memory Testing
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DOI：10.1109/TCSI.2025.3593691.png)
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Abstract
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To achieve high test coverage for scaled-down high-speed memory, the hardware complexity of the algorithmic pattern generator (ALPG) in automatic test equipment (ATE) has increased due to the demands of high-speed operation. However, the potential for further speed-up is constrained by the challenges associated with pipeline insertion and signal integrity preservation. Unlike ALPGs, test patterns in vector memory (VM) are generated by simply fetching pre-stored patterns without performing complex operations. Although its fetching logic is advantageous in high-speed operation, the speed of VM-based pattern generation is limited by the VM load speed. Furthermore, the limited VM capacity restricts the storage of extensive test patterns. To address the limitations of both approaches, a vector memory using bit-level address segmentation (VASE) that enables high-speed memory testing is proposed. VASE improves pattern generation speed by cyclically reusing test patterns while reducing the required VM capacity. Although VASE may impose some limitations on test algorithm coverage and incur overhead in logic area and power consumption, it still supports a wide range of commonly used test algorithms. Considering the speed improvements achieved, these trade-offs are acceptable for ATE applications.
Keywords:
Testing
Logic
Generators
Arithmetic
Vectors
Time complexity
Random access memory
Memory management
Signal integrity
Test pattern generators
Automatic test equipment
high-speed memory testing
test pattern iteration
test pattern segmentation
vector memory
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9.7K
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2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)
2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)IF0
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