Vector transfer by self-tested self-synchronization for parallel systems

doi:10.1109/71.790596

Vector transfer by self-tested self-synchronization for parallel systems

1999-01-01

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C. Svensson

DOI：10.1109/71.790596

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Communications between processing elements (PEs) in very large scale parallel systems become more challenging as the function and speed of the PEs improve continuously. Clocked I/O ports may malfunction if data read failure occurs due to clock skew. There are many drawbacks in global clock distribution utilized to reduce the clock skew. This paper addresses a self-tested self-synchronization (STSS) method for vector transfer between PEs. A test signal is added to remove the data read failure. The advantages of this method are: very high data throughout, less power consumption in clock distribution, no constraints on clock skew and system scale, easy in design, less latency. A failure zone concept is used to characterize the behavior of storage elements. By using a jitter injected test signal, a robust vector transfer between PEs with arbitrary clock phases is achieved and the headache problem of the global synchronization is avoided.

Keywords:

parallel systems

VLSI

high speed interconnect

synchronization

retiming

metastability

Vector transfer by self-tested self-synchronization for parallel systems

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