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Very low-complexity hardware interleaver for turbo decoding

delete2007-07-01
delete17
PRE
AI
Z
Zhongfeng Wang *
Q
Qingwei Li
DOI：10.1109/TCSII.2007.895313delete
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Abstract

Abstract

En 中文
This brief presents a very low complexity hardware interleaver implementation for turbo code in wideband CDMA (W-CDMA) systems. Algorithmic transformations are extensively exploited to reduce the computation complexity and latency. Novel VLSI architectures are developed. The hardware implementation results show that an entire turbo interleave pattern generation unit consumes only 4 k gates, which is an order of magnitude smaller than conventional designs.
Keywords:
CDMA
interleaver
turbo codes
VLSI architecture
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Journal

I
IEEE Transactions on Circuits and Systems and Express Briefs
IF:
4.9
Papers:
8.8K
Citations:
2.5W

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