VLSI architectures for the MAP algorithm

Emmanuel Boutillon

doi:10.1109/TCOMM.2003.809247

VLSI architectures for the MAP algorithm

2003-02-01

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DOI：10.1109/TCOMM.2003.809247

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This paper presents several techniques for the very large-scale integration (VLSI) implementation of the maximum a posteriori (MAP) algorithm. In general, knowledge about the implementation of the Viterbi algorithm can be applied to the MAP algorithm. Bounds are derived for the dynamic range of the state metrics which enable the designer to optimize the word length. The computational kernel of the algorithm is the Add-MAX* operation, which is the Add-Compare-Select operation of the Viterbi algorithm with an added offset. We show that the critical path of the algorithm can be reduced if the Add-MAX* operation is reordered into an Offset-Add-Compare-Select operation by adjusting the location of registers. A general scheduling for the MAP algorithm is presented which gives the tradeoffs between computational complexity, latency, and memory size. Some of these architectures eliminate the need for RAM blocks with unusual form factors or can replace the RAM with registers. These architectures are suited to VLSI implementation of turbo decoders.

Keywords:

forward-backward algorithm

MAP estimation

turbo codes

very large-scale integration (VLSI)

Viterbi decoding

VLSI architectures for the MAP algorithm

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