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Write Pattern Format Algorithm for Reliable NAND-Based SSDs
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DOI：10.1109/TCSII.2014.2327332.png)
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Abstract
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This brief presents and evaluates a pre-coding algorithm to reduce power consumption and improve data retention in NAND-based solid-state drives. Compared to the state-of-the-art asymmetric coding and stripe pattern elimination algorithm, the proposed write pattern format algorithm (WPFA) achieves better data retention while consuming less power. The hardware for WPFA is simpler and requires less circuitry. The performance of WPFA is evaluated by both computer simulations and field-programmable gate array implementation.
Keywords:
NAND flash memory
power consumption
reliability
solid-state drive (SSD)
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