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ZEC ECC: A Zero-Byte Eliminating Compression-Based ECC Scheme for DRAM Reliability
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DOI：10.1109/ACCESS.2024.3431209.png)
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Abstract
En 中文
As DRAM cells continue to shrink, the conventional single error correction and double error detection (SECDED) code is not sufficient to provide DRAM error resilience. To satisfy DRAM reliability demands, various studies have proposed multi-bit error correctable ECC schemes with substantial performance and/or storage overhead compared to the SECDED code. In this paper, we propose ZEC ECC, a zero-byte eliminating compression based ECC scheme, which provides much stronger error correction capability with negligible performance overhead and no storage overhead. ZEC ECC exploits our proposed Zero-byte Eliminating Compression (ZEC) to make room for additional parity bits. Depending on the compression ratio of a memory block (>= 60%, >= 50%, and < 50%), ZEC ECC adaptively selects one out of three different ECC schemes (BCH(32,16,3), BCH(27,16,2), and BCH (573,512,6), respectively). Moreover, ZEC ECC tolerates a single chip failure by exploiting bitwise interleaving data placement, as long as the compression ratio is higher than or equal to 50% for a 64B memory block. Our experimental results show that ZEC ECC reduces the system failure probability (caused by DRAM errors) by 74.4%, on average, with only 1.6% performance overhead and no storage overhead compared to the conventional SECDED.
Keywords:
Error correction codes
Random access memory
Reliability
Codes
Data compression
Error correction
Retirement
DRAM chips
DRAM reliability
data compression
error correction code
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3.6
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9.8W
Citations:
29.4W
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Cited Papers
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