Shen‐Fu Hsiao - Publications, H-index & Citations

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Shen‐Fu Hsiao

national sun yat sen university

18H-index

119Paper Count

1.1KCitation Count

Published Papers 15

Publication Date

A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2022-12-01

PREAI

Wang, Chua-Chin; Sangalang, Ralph Gerard B.; Kuo, Chien-Ping; Wu, Hsin-Che; Hsu, Yi; Hsiao, Shen-Fu; Yeh, Chia-Hung

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Design of a Sparsity-Aware Reconfigurable Deep Learning Accelerator Supporting Various Types of Operations

IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS

IF3.8

2020-09-01

PREAI

Hsiao, Shen-Fu; Chen, Kun-Chih; Lin, Chih-Chien; Chang, Hsuan-Jui; Tsai, Bo-Ching

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Hierarchical Multipartite Function Evaluation

IEEE TRANSACTIONS ON COMPUTERS

IF3.8

2017-01-01

PREAI

Hsiao, Shen-Fu; Wen, Chia-Sheng; Chen, Yi-Hau; Huang, Kuei-Chun

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Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2015-05-01

PREAI

Hsiao, Shen-Fu; Wu, Po-Han; Wen, Chia-Sheng; Meher, Pramod Kumar

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Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2013-05-01

PREAI

Hsiao, Shen-Fu; Jian, Jun-Hong Zhang; Chen, Ming-Chih

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Two-Level Hardware Function Evaluation Based on Correction of Normalized Piecewise Difference Functions

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2012-05-01

PREAI

Hsiao, Shen-Fu; Ko, Hou-Jen; Wen, Chia-Sheng

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Design and Application of Faithfully Rounded and Truncated Multipliers With Combined Deletion, Reduction, Truncation, and Rounding

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2011-05-01

PREAI

Ko, Hou-Jen; Hsiao, Shen-Fu

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Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2010-01-01

PREAI

Hsiao, Shen-Fu; Tsai, Ming-Yu; Wen, Chia-Sheng

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Memory-free low-cost designs of advanced encryption standard using common subexpression elimination for subfunctions in transformations

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2006-03-01

PREAI

Hsiao, SF; Chen, MC; Tu, CS

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Efficient VLSI implementations of fast multiplierless approximated DCT using parameterized hardware modules for silicon intellectual property designlk

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2005-08-01

PREAI

Hsiao, SF; Hu, YH; Juang, TB; Lee, CH

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Low-error carry-free fixed-width multipliers with low-cost compensation circuits

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2005-06-01

PREAI

Juang, TB; Hsiao, SF

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Para-CORDIC: Parallel CORDIC rotation algorithm

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2004-08-01

PREAI

Juang, TB; Hsiao, SF; Tsai, MY

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A memory-efficient and high-speed sine/cosine generator based on parallel CORDIC rotations

ieee signal processing magazine

IF3.9

2004-02-01

OAAI

Hsiao, SF; Hu, YH; Juang, TB

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VLSI design of an efficient embedded zerotree wavelet coder with function of digital watermarking

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS

IF10.9

2000-01-01

PREAI

Hsiao, SF; Tai, YC; Chang, KH

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A cost-efficient and fully-pipelinable architecture for DCT/IDCT

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS

IF10.9

1999-01-01

PREAI

Hsiao, SF; Shiue, WR; Tseng, JM

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Research Directions