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Aditya Anshul

indian institute of technology system (iit system)

6H-index
42Paper Count
91Citation Count
Published Papers 11
Publication Date
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High-Level Synthesis-Based Forensic Watermarking of Hardware IPs Using IP Vendor's DNA Signature
errIEEE Embedded Systems Letters
IF2
err2026-02-01
err0
PREAI
errSengupta, Anirban; Bhui, Nabendu; Anshul, Aditya
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Exploring low overhead fingerprint biometric watermark for loop pipelined hardware IPs during behavioral synthesis
errJOURNAL OF INFORMATION SECURITY AND APPLICATIONS
IF3.7
err2025-05-01
err0
PREAI
errSengupta, Anirban; Anshul, Aditya
errShare
errSave
Bio-mimicking DNA fingerprint profiling for HLS watermarking to counter hardware IP piracy
errSCIENTIFIC REPORTS
IF3.9
err2024-09-28
err0
errOAAI
errSengupta, Anirban; Bhui, Nabendu; Anshul, Aditya; Chourasia, Vishal
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errSave
Securing Reusable IP Cores Using Voice Biometric Based Watermark
errIEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING
IF7.5
err2024-07-01
err0
PREAI
errRathor, Mahendra; Anshul, Aditya; Sengupta, Anirban
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errSave
Secure hardware IP of GLRT cascade using color interval graph based embedded fingerprint for ECG detector
errSCIENTIFIC REPORTS
IF3.9
err2024-06-10
err2
errOAAI
errSengupta, Anirban; Anshul, Aditya
errShare
errSave
Watermarking Hardware IPs Using Design Parameter Driven Encrypted Dispersion Matrix With Eigen Decomposition Based Security Framework
errIEEE ACCESS
IF3.6
err2024-01-01
err2
PREAI
errSengupta, Anirban; Anshul, Aditya
errShare
errSave
Exploring Handwritten Signature Image Features for Hardware Security
errIEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING
IF7.5
err2023-09-01
err0
PREAI
errRathor, Mahendra; Sengupta, Anirban; Chaurasia, Rahul; Anshul, Aditya
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errSave
PSO based exploration of multi-phase encryption based secured image processing filter hardware IP core datapath during high level synthesis
errEXPERT SYSTEMS WITH APPLICATIONS
IF7.5
err2023-08-01
err6
PREAI
errAnshul, Aditya; Sengupta, Anirban
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errSave
Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores
errCOMPUTERS & ELECTRICAL ENGINEERING
IF4.9
err2023-01-01
err4
PREAI
errRathor, Mahendra; Anshul, Aditya; Bharath, K.; Chaurasia, Rahul; Sengupta, Anirban
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A Survey of High Level Synthesis Based Hardware Security Approaches for Reusable IP Cores [Feature]
errIEEE CIRCUITS AND SYSTEMS MAGAZINE
IF3.5
err2023-01-01
err2
PREAI
errAnshul, Aditya; Sengupta, Anirban
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errSave
Palmprint Biometric Versus Encrypted Hash Based Digital Signature for Securing DSP Cores Used in CE Systems
errIEEE CONSUMER ELECTRONICS MAGAZINE
IF4.1
err2022-09-01
err1
PREAI
errChaurasia, Rahul; Anshul, Aditya; Sengupta, Anirban; Gupta, Shikha
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errSave

Research Directions

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Co-authors
Cooperation Journals
A
Anirban Sengupta
H-index: 23 · Papers: 291
M
Mahendra Rathor
H-index: 9 · Papers: 58
S
Shikha Gupta
H-index: 7 · Papers: 25
R
Rahul Chaurasia
H-index: 7 · Papers: 55
V
Vishal Chourasia
H-index: 2 · Papers: 20
View more