Anindya Sundar Dhar - Publications, H-index & Citations

Anindya Sundar Dhar

iit kharagpur, kharagpur, west bengal, india

15H指数

145论文数

999被引数

收录论文 17

发表时间

Performance evaluation for accelerated and efficient prediction of different regression models aggravated with BPSO for enhancing area efficiency through state encoding in sequential circuits

SWARM AND EVOLUTIONARY COMPUTATION

IF8.5

2025-04-01

PREAI

Khatua, Kaushik; Chattopadhyay, Santanu; Dhar, Anindya Sundar

Further Results on the Zero Redundancy Sparse Arrays for DOA Estimation 关于零冗余稀疏阵列用于DOA估计的进一步结果

ieee signal processing magazine

IF3.9

2025-01-01

PREAI

Rajen Kumar Patra; Anindya Sundar Dhar

A Fast Algorithm for Computation of General Integer-Order Hankel Transforms 一种计算一般整数阶Hankel变换的快速算法

ieee signal processing magazine

IF3.9

2025-01-01

PREAI

Amitava Ghosh; Anindya S. Dhar; Indrajit Chakrabarti

ACBAM-Accuracy-Configurable Sign Inclusive Broken Array Booth Multiplier Design

IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING

IF5.4

2022-10-01

PREAI

Roy, Avishek Sinha; Agrawal, Hardik; Dhar, Anindya Sundar

FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion

JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING

IF4

2022-09-01

PREAI

Palchaudhuri, Ayan; Anand, Digvijay; Dhar, Anindya Sundar

A Novel k-times Extended Coprime Array for DOA Estimation With Increased Degrees of Freedom

ieee signal processing magazine

IF3.9

2022-01-01

PREAI

Patra, Rajen Kumar; Dhar, Anindya Sundar

Novel Moving Coprime Array Configurations for Real-Valued Sources

ieee signal processing magazine

IF3.9

2022-01-01

PREAI

Patra, Rajen Kumar; Dhar, Anindya Sundar

Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support

JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING

IF4

2021-05-01

PREAI

Palchaudhuri, Ayan; Dhar, Anindya Sundar

A Novel Nested Array for Real-Valued Sources Exploiting Array Motion

ieee signal processing magazine

IF3.9

2021-01-01

PREAI

Patra, Rajen Kumar; Dhar, Anindya Sundar

SIBAMx2014;Sign Inclusive Broken Array Multiplier Design for Error Tolerant Applications SIBAMx2014; 用于容错应用的符号包含断开阵列乘法器设计

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2020-11-01

PREAI

Roy, Avishek Sinha; Dhar, Anindya Sundar

Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies

JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING

IF4

2019-08-01

PREAI

Palchaudhuri, Ayan; Dhar, Anindya Sundar

A Variable RF Carrier Modulation Scheme for Ultralow Power Wireless Body-Area Network 一种用于超低功耗无线体域网的可变射频载波调制方案

ieee open journal of circuits and systems

IF4.4

2012-06-01

PREAI

Ghosh, Amitava; Halder, Achintya; Dhar, Anindya S.

VLSI architecture for low latency radix-4 CORDIC

COMPUTERS & ELECTRICAL ENGINEERING

IF4.9

2011-11-01

PREAI

Lakshmi, B.; Dhar, A. S.

Integrated voice and data transmission employing adaptive modulation in wireless networks

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS

IF3.2

2009-12-01

PREAI

Mahapatra, Rajarshi; Dhar, Anindya Sundar; Datta, Debasish

Adaptive digital phase modulation schemes using transition-initiated phase acceleration

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS

IF3.2

2008-11-01

PREAI

Mahapatra, Rajarshi; Dhar, Anindya Sundar; Datta, Debasish

A trigonometric formulation of the LMS algorithm for realization on pipelined CORDIC

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2005-09-01

PREAI

Chakraborty, M; Dhar, AS; Lee, MH

A VLSI array architecture for realization of DFT, DHT, DCT and DST

SIGNAL PROCESSING

IF3.6

2001-09-01

OAAI

Maharatna, K; Dhar, AS; Banerjee, S

研究方向