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H
Hsie-Chia Chang
National Yang Ming Chiao Tung University
23
H指数
134
论文数
1.6K
被引数
0
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19
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A (21150,19050) GC-LDPC Decoder for NAND Flash Applications
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF
5.2
2019-03-01
27
PRE
AI
Liao, Yen-Chin; Lin, Chien; Chang, Hsie-Chia; Lin, Shu
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An Improved DPA Countermeasure Based on Uniform Distribution Random Power Generator for IoT Applications
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF
5.2
2017-09-01
8
PRE
AI
Chung, Szu-Chi; Yu, Chun-Yuan; Lee, Sung-Shine; Chang, Hsie-Chia; Lee, Chen-Yi
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An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF
4.9
2016-09-01
19
PRE
AI
Lin, Chia-Lung; Tu, Shu-Wen; Chen, Chih-Lung; Chang, Hsie-Chia; Lee, Chen-Yi
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Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF
5.2
2015-10-01
2
PRE
AI
Lin, Chia-Lung; Chen, Chih-Lung; Chang, Hsie-Chia; Lee, Chen-Yi
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An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF
4.9
2015-03-01
3
PRE
AI
Lee, Xin-Ru; Yang, Chih-Wen; Chen, Chih-Lung; Chang, Hsie-Chia; Lee, Chen-Yi
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A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF
5.2
2015-02-01
42
PRE
AI
Lee, Xin-Ru; Chen, Chih-Lung; Chang, Hsie-Chia; Lee, Chen-Yi
分享
收藏
An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo Decoder
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF
4.9
2015-01-01
2
PRE
AI
Lin, Chen-Yang; Wong, Cheng-Chi; Chang, Hsie-Chia
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A 2.56 Gb/s Soft RS (255,239) Decoder Chip for Optical Communication Systems
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF
5.2
2014-07-01
12
OA
AI
Lin, Yi-Min; Hsu, Chih-Hsiang; Chang, Hsie-Chia; Lee, Chen-Yi
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Iterative Decoding Algorithms for a Class of Non-Binary Two-Step Majority-Logic Decodable Cyclic Codes
IEEE TRANSACTIONS ON COMMUNICATIONS
IF
8.3
2014-06-01
0
PRE
AI
Chang, Hsiu-Chi; Chang, Hsie-Chia
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Integrating Non-Repetitive LT Encoders With Modified Distribution to Achieve Unequal Erasure Protection
IEEE TRANSACTIONS ON MULTIMEDIA
IF
9.7
2013-12-01
10
PRE
AI
Yen, Kuo-Kuang; Liao, Yen-Chin; Chen, Chih-Lung; Zao, John K.; Chang, Hsie-Chia
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An Iterative Weighted Reliability Decoding Algorithm for Two-Step Majority-Logic Decodable Cyclic Codes
IEEE COMMUNICATIONS LETTERS
IF
4.4
2013-10-01
1
PRE
AI
Chang, Hsiu-Chi; Chen, Chih-Lung; Chang, Hsie-Chia
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Modified Robust Soliton Distribution (MRSD) with Improved Ripple Size for LT Codes
改进的鲁棒孤子分布 (MRSD),用于LT码的纹波大小
IEEE COMMUNICATIONS LETTERS
IF
4.4
2013-05-01
32
PRE
AI
Yen, Kuo-Kuang; Liao, Yen-Chin; Chen, Chih-Lung; Chang, Hsie-Chia
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An Efficient DPA Countermeasure With Randomized Montgomery Operations for DF-ECC Processor
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF
4.9
2012-05-01
19
OA
AI
Lee, Jen-Wei; Hsiao, Ju-Hung; Chang, Hsie-Chia; Lee, Chen-Yi
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A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF
4.9
2012-02-01
28
PRE
AI
Liu, Po-Chun; Chang, Hsie-Chia; Lee, Chen-Yi
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A MPCN-Based Parallel Architecture in BCH Decoders for NAND Flash Memory Devices
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF
4.9
2011-10-01
15
OA
AI
Lin, Yi-Min; Yang, Chi-Heng; Hsu, Chih-Hsiang; Chang, Hsie-Chia; Lee, Chen-Yi
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High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF
5.2
2011-06-01
18
PRE
AI
Wong, Cheng-Chi; Chang, Hsie-Chia
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A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF
4.9
2010-07-01
41
PRE
AI
Liu, Po-Chun; Chang, Hsie-Chia; Lee, Chen-Yi
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A Universal VLSI Architecture for ReedSolomon Error-and-Erasure Decoders
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF
5.2
2009-09-01
8
PRE
AI
Chang, Hsie-Chia; Lin, Chien-Ching; Chang, Fu-Ke; Lee, Chen-Yi
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New serial architecture for the Berlekamp-Massey algorithm
IEEE TRANSACTIONS ON COMMUNICATIONS
IF
8.3
1999-04-01
22
PRE
AI
Chang, HC; Shung, CB
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S
Shu Lin
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C
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H 指数: 27 · 论文数: 78
C
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H 指数: 20 · 论文数: 67
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H 指数: 12 · 论文数: 30
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