Hsie-Chia Chang - Publications, H-index & Citations

Hsie-Chia Chang

National Yang Ming Chiao Tung University

23H指数

134论文数

1.6K被引数

收录论文 19

发表时间

A (21150,19050) GC-LDPC Decoder for NAND Flash Applications

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2019-03-01

PREAI

Liao, Yen-Chin; Lin, Chien; Chang, Hsie-Chia; Lin, Shu

An Improved DPA Countermeasure Based on Uniform Distribution Random Power Generator for IoT Applications

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2017-09-01

PREAI

Chung, Szu-Chi; Yu, Chun-Yuan; Lee, Sung-Shine; Chang, Hsie-Chia; Lee, Chen-Yi

An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2016-09-01

PREAI

Lin, Chia-Lung; Tu, Shu-Wen; Chen, Chih-Lung; Chang, Hsie-Chia; Lee, Chen-Yi

Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2015-10-01

PREAI

Lin, Chia-Lung; Chen, Chih-Lung; Chang, Hsie-Chia; Lee, Chen-Yi

An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2015-03-01

PREAI

Lee, Xin-Ru; Yang, Chih-Wen; Chen, Chih-Lung; Chang, Hsie-Chia; Lee, Chen-Yi

A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2015-02-01

PREAI

Lee, Xin-Ru; Chen, Chih-Lung; Chang, Hsie-Chia; Lee, Chen-Yi

An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo Decoder

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2015-01-01

PREAI

Lin, Chen-Yang; Wong, Cheng-Chi; Chang, Hsie-Chia

A 2.56 Gb/s Soft RS (255,239) Decoder Chip for Optical Communication Systems

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2014-07-01

OAAI

Lin, Yi-Min; Hsu, Chih-Hsiang; Chang, Hsie-Chia; Lee, Chen-Yi

Iterative Decoding Algorithms for a Class of Non-Binary Two-Step Majority-Logic Decodable Cyclic Codes

IEEE TRANSACTIONS ON COMMUNICATIONS

IF8.3

2014-06-01

PREAI

Chang, Hsiu-Chi; Chang, Hsie-Chia

Integrating Non-Repetitive LT Encoders With Modified Distribution to Achieve Unequal Erasure Protection

IEEE TRANSACTIONS ON MULTIMEDIA

IF9.7

2013-12-01

PREAI

Yen, Kuo-Kuang; Liao, Yen-Chin; Chen, Chih-Lung; Zao, John K.; Chang, Hsie-Chia

An Iterative Weighted Reliability Decoding Algorithm for Two-Step Majority-Logic Decodable Cyclic Codes

IEEE COMMUNICATIONS LETTERS

IF4.4

2013-10-01

PREAI

Chang, Hsiu-Chi; Chen, Chih-Lung; Chang, Hsie-Chia

Modified Robust Soliton Distribution (MRSD) with Improved Ripple Size for LT Codes 改进的鲁棒孤子分布 (MRSD)，用于LT码的纹波大小

IEEE COMMUNICATIONS LETTERS

IF4.4

2013-05-01

PREAI

Yen, Kuo-Kuang; Liao, Yen-Chin; Chen, Chih-Lung; Chang, Hsie-Chia

An Efficient DPA Countermeasure With Randomized Montgomery Operations for DF-ECC Processor

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2012-05-01

OAAI

Lee, Jen-Wei; Hsiao, Ju-Hung; Chang, Hsie-Chia; Lee, Chen-Yi

A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2012-02-01

PREAI

Liu, Po-Chun; Chang, Hsie-Chia; Lee, Chen-Yi

A MPCN-Based Parallel Architecture in BCH Decoders for NAND Flash Memory Devices

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2011-10-01

OAAI

Lin, Yi-Min; Yang, Chi-Heng; Hsu, Chih-Hsiang; Chang, Hsie-Chia; Lee, Chen-Yi

High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2011-06-01

PREAI

Wong, Cheng-Chi; Chang, Hsie-Chia

A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2010-07-01

PREAI

Liu, Po-Chun; Chang, Hsie-Chia; Lee, Chen-Yi

A Universal VLSI Architecture for ReedSolomon Error-and-Erasure Decoders

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2009-09-01

PREAI

Chang, Hsie-Chia; Lin, Chien-Ching; Chang, Fu-Ke; Lee, Chen-Yi

New serial architecture for the Berlekamp-Massey algorithm

IEEE TRANSACTIONS ON COMMUNICATIONS

IF8.3

1999-04-01

PREAI

Chang, HC; Shung, CB

研究方向