Eduardo de la Torre - Publications, H-index & Citations

Eduardo de la Torre

Universidad Politecnica de Madrid

21H指数

144论文数

1.6K被引数

收录论文 16

发表时间

Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs

IEEE TRANSACTIONS ON COMPUTERS

IF3.8

2022-11-01

PREAI

Rodriguez, Alfonso; Otero, Andres; Platzner, Marco; de la Torre, Eduardo

Multi-grain reconfigurable and scalable overlays for hardware accelerator composition

JOURNAL OF SYSTEMS ARCHITECTURE

IF4.1

2021-12-01

OAAI

Zamacola, Rafael; Otero, Andres; de la Torre, Eduardo

A Machine-Learning-Based Distributed System for Fault Diagnosis With Scalable Detection Quality in Industrial IoT

IEEE INTERNET OF THINGS JOURNAL

IF8.9

2021-03-15

PREAI

Marino, Rodrigo; Wisultschew, Cristian; Otero, Andres; Lanza-Gutierrez, Jose M.; Portilla, Jorge; de la Torre, Eduardo

Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs

IEEE ACCESS

IF3.6

2020-01-01

OAAI

Suriano, Leonardo; Otero, Andres; Rodriguez, Alfonso; Sanchez-Renedo, Manuel; De la Torre, Eduardo

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems 基于FPGA的多粒度可重构系统设计的集成方法和工具支持

IEEE ACCESS

IF3.6

2020-01-01

OAAI

Zamacola, Rafael; Otero, Andres; Garcia, Alberto; De La Torre, Eduardo

Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation

IEEE ACCESS

IF3.6

2020-01-01

OAAI

Perez, Arturo; Rodriguez, Alfonso; Otero, Andres; Gonzalez Arjona, David; Jimenez-Peralo, Alvaro; Angel Verdugo, Miguel; De La Torre, Eduardo

Memory sequencing reveals heritable single cell gene expression programs associated with therapy resistance

CANCER RESEARCH

IF16.6

2019-07-01

PREAI

Shaffer, Sydney; Emert, Benjamin; Torre, Eduardo; Raj, Arjun

Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression 可扩展的基于硬件的板载处理，用于运行时自适应无损高光谱压缩

IEEE ACCESS

IF3.6

2019-01-01

OAAI

Rodriguez, Alfonso; Santos, Lucana; Sarmiento, Roberto; De La Torre, Eduardo

FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework

SENSORS

IF3.5

2018-06-08

OAAI

Rodriguez, Alfonso; Valverde, Juan; Portilla, Jorge; Otero, Andres; Riesgo, Teresa; de la Torre, Eduardo

Introduction to the Special Section on FPGAs Technology and Applications

COMPUTERS & ELECTRICAL ENGINEERING

IF4.9

2016-01-01

PREAI

Cumplido, Rene; Athanas, Peter; de la Torre, Eduardo

Introduction to the special issue on FPGA Technology and Applications

COMPUTERS & ELECTRICAL ENGINEERING

IF4.9

2014-05-01

PREAI

Athanas, Peter; Cumplido, Rene; de la Torre, Eduardo

Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing 自适应图像处理的自重构演化硬件系统

IEEE TRANSACTIONS ON COMPUTERS

IF3.8

2013-08-01

PREAI

Salvador, Ruben; Otero, Andres; Mora, Javier; de la Torre, Eduardo; Riesgo, Teresa; Sekanina, Lukas

Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks

SENSORS

IF3.5

2012-02-28

OAAI

Valverde, Juan; Otero, Andres; Lopez, Miguel; Portilla, Jorge; de la Torre, Eduardo; Riesgo, Teresa

Embedded Runtime Reconfigurable Nodes for Wireless Sensor Networks Applications

IEEE SENSORS JOURNAL

IF4.5

2011-09-01

PREAI

Esteves Krasteva, Yana; Portilla, Jorge; de la Torre, Eduardo; Riesgo, Teresa

Reconfigurable Networks on Chip: DRNoC architecture 可重构片上网络: DRNoC架构

JOURNAL OF SYSTEMS ARCHITECTURE

IF4.1

2010-07-01

PREAI

Krasteva, Yana E.; de la Torre, Eduardo; Riesgo, Teresa

Design methodologies based on hardware description languages 基于硬件描述语言的设计方法

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

IF7.2

1999-01-01

PREAI

Riesgo, T; Torroja, Y; de la Torre, E

研究方向