未登录Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102,400 nodes
Sugie, Yuya; Yoshida, Yuki; Mertig, Normann; Takemoto, Takashi; Teramoto, Hiroshi; Nakamura, Atsuyoshi; Takigawa, Ichigaku; Minato, Shin-ichi; Yamaoka, Masanao; Komatsuzaki, Tamiki
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