Vishnu P. Nambiar - Publications, H-index & Citations

Vishnu P. Nambiar

Universiti Teknologi Malaysia

12H指数

46论文数

339被引数

收录论文 9

发表时间

0.08mm2 128nW MFCC Engine for Ultra-low Power, Always-on Smart Sensing Applications

2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22)

IF0

2022-05-28

OAAI

Chong, Yi Sheng; Goh, Wang Ling; Ong, Yew Soon; Nambiar, Vishnu P.; Anh Tuan Do

A 2.5 μW KWS Engine With Pruned LSTM and Embedded MFCC for IoT Applications

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2022-03-01

PREAI

Chong, Y. S.; Goh, W. L.; Nambiar, V. P.; Do, A. T.

A 5.28-mm2 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2021-12-01

OAAI

Pu, Junran; Goh, Wang Ling; Nambiar, Vishnu P.; Wong, Ming Ming; Tuan, Anh

Energy Efficient 0.5V 4.8pJ/SOP 0.93μW Leakage/Core Neuromorphic Processor Design

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2021-09-01

OAAI

Nambiar, Vishnu P.; Pu, Junran; Lee, Yun Kwan; Mani, Aarthy; Koh, Eng Kiat; Wong, Ming Ming; Li, Fei; Goh, Wang Ling; Anh Tuan Do

A Low-Cost High-Throughput Digital Design of Biorealistic Spiking Neuron 生物掺加神经元的低成本高通量数字设计

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2021-04-01

PREAI

Pu, Junran; Goh, Wang Ling; Nambiar, Vishnu P.; Chong, Yi Sheng; Do, Anh Tuan

A Low Power and Low Area Router With Congestion-Aware Routing Algorithm for Spiking Neural Network Hardware Implementations 具有拥塞感知路由算法的低功耗和低区域路由器，用于尖峰神经网络硬件实现

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2021-01-01

PREAI

Pu, Junran; Goh, Wang Ling; Nambiar, Vishnu P.; Anh Tuan Do

Optimization of structure and system latency in evolvable block-based neural networks using genetic algorithm 基于遗传算法的进化块神经网络结构和系统延迟优化

NEUROCOMPUTING

IF6.5

2014-12-01

PREAI

Nambiar, Vishnu P.; Khalil-Hani, Mohamed; Marsono, M. N.; Sia, C. W.

Hardware implementation of evolvable block-based neural networks utilizing a cost efficient sigmoid-like activation function

NEUROCOMPUTING

IF6.5

2014-09-01

PREAI

Nambiar, Vishnu P.; Khalil-Hani, Mohamed; Sahnoun, Riadh; Marsono, M. N.

HW/SW co-design of reconfigurable hardware-based genetic algorithm in FPGAs applicable to a variety of problems

COMPUTING

IF2.8

2013-02-21

PREAI

Nambiar, Vishnu P.; Balakrishnan, Sathivellu; Khalil-Hani, Mohamed; Marsono, M. N.

研究方向