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Tsung-Yi Ho

the chinese university of hong kong

41H指数
532论文数
6.6K被引数
收录论文 43
发表时间
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G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner using Task Graph ParallelismG-kway：基于任务图并行的高效多级GPU加速k路图划分器
errACM Transactions on Design Automation of Electronic Systems
IF2
err2026-05-01
err0
PREAI
errLee, Wan Luan; Lin, Dian-Lun; Jiang, Shui; Chiu, Cheng-Hsiang; Lin, Yibo; Yu, Bei; Ho, Tsung-Yi; Huang, Tsung-Wei
err分享
err收藏
CD-LLM: A Heterogeneous Multi-FPGA System for Batched Decoding of 70B+LLMs Using a Compute-Dedicated ArchitectureCD-LLM：一种用于批处理解码70B+LLM的计算专用异构多FPGA系统
errACM Transactions on Reconfigurable Technology and Systems
IF2.8
err2026-03-01
err0
PREAI
errMa, Wenheng; Yang, Xinhao; Zeng, Shulin; Liu, Tengxuan; Shen, Libo; Wang, Hongyi; Li, Shiyao; Hong, Ke; Zhu, Zhenhua; Ning, Xuefei; Ho, Tsung-Yi; Dai, Guohao; Wang, Yu
err分享
err收藏
Adaptive Redistribution Layer Routing for Chiplet-Package Co-Design in 2.5D System2.5D系统中针对芯片封装协同设计的自适应 Redistribution Layer 布线
errACM Transactions on Design Automation of Electronic Systems
IF2
err2026-02-01
err0
PREAI
errZh, Zhen; Hung, Weishiun; Kabir, Md Arafat; Peng, Yarui; Ho, Tsung-Yi
err分享
err收藏
CHOP: Clustered Hybrid Optimization for Logic Synthesis With Self-Supervised PredictionCHOP：用于逻辑综合的聚类混合优化与自监督预测
errIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IF2.9
err2026-01-05
err0
PREAI
errRongliang Fu; Ran Zhang; Ziyang Zheng; Zhengyuan Shi; Yuan Pu; Junying Huang; Bei Yu; Qiang Xu; Tsung-Yi Ho
err分享
err收藏
Design Automation Techniques for Microfluidic Fully Programmable Valve Array Biochips: A Systematic Survey微流控全可编程阀门阵列生物芯片的设计自动化技术：一项系统综述
errACM Transactions on Design Automation of Electronic Systems
IF2
err2026-01-01
err0
PREAI
errQi, Shuang; Yu, Zhiwen; Guo, Bin; Li, Sizhao; Li, Zipeng; Ma, Hanbin; Ho, Tsungyi; Chakrabarty, Krishnendu; Huang, Xing
err分享
err收藏
Adaptive Control-Logic Routing with Length Matching and Fault Tolerance for FPVA Biochips Using Deep Reinforcement Learning基于深度强化学习的FPVA生物芯片的自适应控制逻辑路由与长度匹配及容错技术
errACM Transactions on Design Automation of Electronic Systems
IF2
err2026-01-01
err0
PREAI
errCai, Huayang; Liu, Genggeng; Guo, Wenzhong; Li, Zipeng; Ho, Tsungyi; Huang, Xing
err分享
err收藏
SimPart: A Simple Yet Effective Replication-Aided Partitioning Algorithm for Logic Simulation on GPUSimPart：一种简单而有效的用于GPU逻辑仿真中的复制辅助分区算法
errEURO-PAR 2025: PARALLEL PROCESSING, PT III
IF0
err2026-01-01
err0
PREAI
errChung, Yi-Hua; Jiang, Shui; Lee, Wan-Luan; Zhang, Yanqing; Ren, Haoxing; Ho, Tsung-Yi; Huang, Tsung-Wei
err分享
err收藏
Efficient Routing-Based Synthesis for Digital Microfluidic Biochips via Reinforcement Learning基于强化学习的数字微流控生物芯片高效路由合成
errIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IF2.9
err2026-01-01
err0
PREAI
errLiu, Biao; Jiang, Chen; Xu, Qi; Yao, Hailong; Ho, Tsung-Yi; Yuan, Bo
err分享
err收藏
Parallel Delay-Driven Layer Assignment Leveraging Hierarchical Task Graph Modeling for Advanced Technology Nodes基于层次化任务图建模的并行延迟驱动层分配方法，用于先进工艺节点
errIEEE Transactions on Computers
IF3.8
err2025-12-16
err0
PREAI
errZepeng Li; Zhen Zhuang; Genggeng Liu; Wen-Hao Liu; Tsung-Yi Ho; Ting-Chi Wang
err分享
err收藏
Ckt2Vec: Efficient Electrical Encoding for Analog Circuit Representations in Vector SpaceCkt2Vec：用于模拟电路表示的向量空间高效电气编码
errIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IF2.9
err2025-12-11
err0
PREAI
errPeng Xu; Yapeng Li; Tinghuan Chen; Tsung-Yi Ho; Bei Yu
err分享
err收藏
Pac-PIM: A Parallel Communication Framework for Commodity Processing-in-memory SystemsPac-PIM：面向商用处理内存储器系统的并行通信框架
errACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION
IF1.8
err2025-12-01
err0
PREAI
errYang, Fan; Zhou, Zhe; Li, Cong; Ho, Tsung-Yi; Yang, Ming-Chang
err分享
err收藏
JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum CircuitsJPnR: 一种用于单磁通量子电路的长度匹配布局布线框架
errIEEE Transactions on Computers
IF3.8
err2025-11-10
err0
PREAI
errRongliang Fu; Minglei Zhou; Siyan Chen; Xinda Chen; Junying Huang; Xiaochun Ye; Zhimin Zhang; Tsung-Yi Ho
err分享
err收藏
RankTuner: When Design Tool Parameter Tuning Meets Preference Bayesian OptimizationRankTuner：当设计工具参数调优遇到偏好贝叶斯优化
errIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IF2.9
err2025-11-04
err0
PREAI
errPeng Xu; Su Zheng; Yuyang Ye; Chen Bai; Siyuan Xu; Hao Geng; Tsung-Yi Ho; Bei Yu
err分享
err收藏
Selecting Nets to Rip Up and Reroute via SAT通过SAT选择要拆解和重布的网
errIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IF2.9
err2025-09-18
err0
PREAI
errHongduo Liu; Siting Liu; Zhongdong Qi; Tsung-Yi Ho; Bei Yu
err分享
err收藏
Intelligent single-cell manipulation: LLMs- and object detection-enhanced active-matrix digital microfluidics智能单细胞操控：基于LLMs和目标检测增强的主动矩阵式数字微流控技术
errMicrosystems & Nanoengineering
IF9.9
err2025-07-07
err0
errOAAI
errZhiqiang Jia; Chen Jiang; Jiahao Li; Yacine Belgaid; Mingfeng Ge; Li Li; Siyi Hu; Xing Huang; Tsung-Yi Ho; Wenfei Dong; Zhiwen Yu; Hanbin Ma
err分享
err收藏
Path-Driven Washing and Drying Co-Optimization in Continuous-Flow Lab-on-Chips连续流芯片实验室中路径驱动的洗涤和干燥协同优化
errIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IF2.9
err2025-06-18
err0
PREAI
errXing Huang; Jiaxuan Wang; Zhiwen Yu; Bin Guo; Hanbin Ma; Tsung-Yi Ho; Ulf Schlichtmann; Krishnendu Chakrabarty
err分享
err收藏
HiePlace: Efficient Hierarchical PCB Placement
errIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IF2.9
err2025-06-17
err0
PREAI
errShanyi Li; Zhen Zhuang; Mingyu Liu; Weihua Sheng; Bei Yu; Tsung-Yi Ho
err分享
err收藏
InstantGR: Scalable GPU Parallelization for 3-D Global Routing
errIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IF2.9
err2025-05-26
err0
errOAAI
errLiang Xiao; Shiju Lin; Jinwei Liu; Qinkai Duan; Tsung-Yi Ho; Evangeline F. Y. Young
err分享
err收藏
PRO-TIME: Prerouting Optimization-Aware Timing Prediction via Multimodal LearningPRO-TIME：基于多模态学习的预路由优化感知时序预测
errIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IF2.9
err2025-05-12
err0
PREAI
errZiyi Wang; Siting Liu; Yuan Pu; Song Chen; Tsung-Yi Ho; Bei Yu
err分享
err收藏
Hierarchical Partitioning-Based Interchip Redistribution Layer Routing for Fan-Out Wafer-Level Packaging基于层次化划分的扇出晶圆级封装芯片间重组层布线
errIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IF2.9
err2025-04-04
err0
PREAI
errHaoyang Xu; Xing Huang; Zhen Zhuang; Zhiwen Yu; Bin Guo; Kai-Yuan Chao; Bei Yu; Tsung-Yi Ho; Martin D. F. Wong
err分享
err收藏

研究方向

暂无研究方向
合作学者
合作期刊
邓
邓初夏 (Chu‐Xia Deng)
H 指数: 134 · 论文数: 833
刘
刘艺 (Yi Liu)
H 指数: 107 · 论文数: 1.7K
Y
Yü Huang
H 指数: 92 · 论文数: 969
K
Krishnendu Chakrabarty
H 指数: 80 · 论文数: 1.4K
C
Chang‐Jin Kim
H 指数: 79 · 论文数: 711
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