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M

Manh Anh

Nanyang Technological University

17H指数
87论文数
1.2K被引数
收录论文 6
发表时间
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A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector具有紧凑型四分之一速率CMOS线性相位检测器的双环时钟和数据恢复电路
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF5.2
err2012-06-01
err24
PREAI
errTan, Yung Sern; Yeo, Kiat Seng; Boon, Chirn Chye; Do, Manh Anh
err分享
err收藏
An Energy-Aware CMOS Receiver Front End for Low-Power 2.4-GHz Applications
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF5.2
err2010-10-01
err33
errOAAI
errDo, Aaron V.; Boon, Chirn Chye; Do, Manh Anh; Yeo, Kiat Seng; Cabuk, Alper
err分享
err收藏
A SPICE COMPATIBLE MODEL OF ON-WAFER COUPLED INTERCONNECTS FOR CMOS RFICS
errPROGRESS IN ELECTROMAGNETICS RESEARCH-PIER
IF9.3
err2010-01-01
err9
errOAAI
errShi, X.; Yeo, K. S.; Lim, W. M.; Do, M. A.; Boon, C. C.
err分享
err收藏
Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF5.2
err2010-01-01
err66
errOAAI
errKrishna, Manthena Vamshi; Do, Manh Anh; Yeo, Kiat Seng; Boon, Chirn Chye; Lim, Wei Meng
err分享
err收藏
An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF5.2
err2008-07-01
err46
errOAAI
errJiang, Shan; Do, Manh Anh; Yeo, Kiat Seng; Lim, Wei Meng
err分享
err收藏
Broad-band design techniques for transimpedance amplifiers
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF5.2
err2007-03-01
err87
errOAAI
errLu, Zhenghao; Yeo, Kiat Seng; Ma, Jianguo; Do, Manh Anh; Lim, Wei Meng; Chen, Xueying
err分享
err收藏

研究方向

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合作学者
合作期刊
K
Kiat Seng Yeo
H 指数: 48 · 论文数: 676
J
Jianguo Ma
H 指数: 41 · 论文数: 378
X
Xueying Chen
H 指数: 38 · 论文数: 371
C
Chirn Chye Boon
H 指数: 34 · 论文数: 209
X
Xiaomeng Shi
H 指数: 31 · 论文数: 176
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