Hirofumi Shinohara

kyoto university

24H指数

214论文数

2.4K被引数

收录论文 7

发表时间

A 236-nW LFSR-Based Asymmetric Clonable PUF Group With Peer-to-Peer Response Equivalence

IEEE Transactions on Circuits and Systems I-Regular Papers

IF5.2

2026-07-09

OAAI

Zhenzhe Chen; Weirong Dong; Kunyang Liu; Quan Cheng; Hirofumi Shinohara; Takashi Sato

A Physically Unclonable Function With Less Than 4.16E--7 BER Featuring Secure In-Cell HCI Burn-In and nMOS-Dominant PUF Data Generation 具有低于4.16E--7误码率且具有安全单元内HCI老化和nMOS主导PUF数据生成的物理不可克隆函数

IEEE Journal of Solid-State Circuits

IF5.6

2026-03-03

PREAI

Kunyang Liu; Zihan Fu; Gen Li; Hongliang Pu; Zhibo Guan; Xingyu Wang; Shufan Xu; Kiichi Niitsu; Hirofumi Shinohara

Entropy Improvement in Latch-Based True Random Number Generator Using Negative Bias Temperature Instability 基于锁存器的真随机数发生器中利用负偏压温度不稳定性的熵改进

ieee transactions on circuits and systems i: regular papers

IF0

2025-10-30

PREAI

Ruilin Zhang; Ye Cao; Haochen Zhang; Quan Cheng; Shinichi Nishizawa; Kiichi Niitsu; Hirofumi Shinohara

De-Correlation and De-Bias Post-Processing Circuits for True Random Number Generator

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2024-11-01

OAAI

Zhang, Ruilin; Zhang, Haochen; Wang, Xingyu; Ziyang, Ye; Liu, Kunyang; Nishizawa, Shinichi; Niitsu, Kiichi; Shinohara, Hirofumi

Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2012-12-01

PREAI

Takahashi, Ryo; Takata, Hidehiro; Yasufuku, Tadashi; Fuketa, Hiroshi; Takamiya, Makoto; Nomura, Masahiro; Shinohara, Hirofumi; Sakurai, Takayasu

Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2011-05-01

PREAI

Pu, Yu; Zhang, Xin; Ikeuchi, Katsuyuki; Muramatsu, Atsushi; Kawasumi, Atsushi; Takamiya, Makoto; Nomura, Masahiro; Shinohara, Hirofumi; Sakurai, Takayasu

A 65-nm CMOS Downconverter-Less Clock Generator Architecture Using Voltage Stacking of Oscillator and Frequency Dividers for Scaling-Friendly IoTs 一种采用振荡器和频率分频器电压叠加技术的65-nm CMOS无下变频时钟发生器架构，适用于可扩展物联网(IoT)设备

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IF3.1

OAAI

You Wu; Kei Awano; Kento Okamura; Teruaki Ono; Kohei Sakamoto; Hiroaki Kitaike; Hironori Tagawa; Jin Nakamura; Masaya Kaneko; Yuta Kimura; Hiroaki Nakamura; Shufan Xu; Ruilin Zhang; Kunyang Liu; Hirofumi Shinohara; Kiichi Niitsu

研究方向