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Shubin Liu

xidian university

19H指数
191论文数
1.5K被引数
收录论文 62
发表时间
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A 56-Gb/s NRZ and 80-Gb/s PAM-4 Receiver with an Analog Decision Feed-Forward Equalizer Achieving up to 22.5-dB Compensation at 28 GHz56-Gb/s NRZ 和 80-Gb/s PAM-4 接收机，采用模拟判决前馈均衡器，在 28 GHz 时实现最高 22.5-dB 补偿
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF4.9
err2026-09-08
err0
PREAI
errXianting Su; Xiaoteng Zhao; Yukui Yu; Miao Zhang; Jie Liu; Hongyu Su; Zhicheng Dong; Shubin Liu; Zhangming Zhu
err分享
err收藏
A 100-Gb/s Hardware-Efficient DPD-Calibrated Resistor-Less Voltage-Mode Transmitter With MUX-Merged Output Stage in 28-nm CMOS100-Gb/s 高效硬件实现的电阻-less 电压模式发射机，采用MUX合并输出级，并在28-nm CMOS工艺中完成DPD校准
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF4.9
err2026-08-06
err0
PREAI
errChenxi Han; Xiaoteng Zhao; Qi Zhang; Yuan Liu; Yuhao Zhang; Hongzhi Liang; Yukui Yu; Shubin Liu; Zhangming Zhu
err分享
err收藏
A 0.054-mm2 Clock Generator With 26-GHz Double-Edge Sampling PLL and 7-bit Multifrequency PI Scoring 42.5-fsrms Jitter and −251.0-dB FoMJ0.054-mm2 时钟发生器，采用 26-GHz 双边沿采样 PLL 和 7 位多频率 PI 校正，抖动为 42.5-fsrms，FoMJ 为 -251.0-dB
errIEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF3.1
err2026-07-30
err0
PREAI
errXianting Su; Xiaoteng Zhao; Zhicheng Dong; Weitan Huang; Yuan Gao; Depeng Sun; Hongzhi Liang; Chenxi Han; Lin Wang; Shubin Liu; Zhangming Zhu
err分享
err收藏
A 112 GS/s 7 b 64× Time-Interleaved Hybrid ADC Achieving 43.1-dB SFDR at 44.1-GHz Input in 28-nm CMOS112 GS/s 7位64×时间交织混合ADC在28纳米CMOS工艺下实现44.1 GHz输入时的43.1 dB SFDR
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF4.9
err2026-07-27
err0
PREAI
errYixiao Luo; Hongzhi Liang; Li Dang; Haolin Han; Yi Shen; Dengquan Li; Shubin Liu; Ruixue Ding; Zhangming Zhu
err分享
err收藏
A 16× Interleaved 32-GS/s 8b Hybrid ADC With Self-Tracking Inter-Stage Gain Achieving 44.3-dB SFDR at 20.9-GHz Input16路交错32-GS/s 8位混合型ADC，通过自跟踪级间增益在20.9-GHz输入时实现44.3-dB SFDR
errIEEE Journal of Solid-State Circuits
IF5.6
err2026-04-17
err0
PREAI
errHongzhi Liang; Jun Chang; Yixiao Luo; Li Dang; Haolin Han; Yi Shen; Dengquan Li; Shubin Liu; Ruixue Ding; Zhangming Zhu
err分享
err收藏
A 12-bit 200-MS/s SAR ADC With Capacitor-Reuse-Based Redundant Weighting Technique一款基于电容器复用冗余加权技术的12位200-MS/s SAR ADC
errieee transactions on circuits and systems ii: express briefs
IF0
err2026-03-02
err0
PREAI
errAngyang Li; Yi Shen; Anji Huang; Shubin Liu; Ruixue Ding; Zhangming Zhu
err分享
err收藏
A Low-Latency Synchronization Header Detector and Hardware-Efficient Correction Decoder for JESD204C Receiver低延迟同步报头检测器及适用于JESD204C接收机的硬件高效校正译码器
errIEEE Transactions on Circuits and Systems I-Regular Papers
IF5.2
err2026-02-01
err0
PREAI
errYin, Peng; Chen, Haoran; Ma, Rui; Zhang, Jinlong; Liu, Mingguo; Hou, Weizhou; Liu, Shubin; Shu, Zhou; Zhu, Zhangming
err分享
err收藏
A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator (Withdrawal of Vol 166, art no 106872, 2025)一种56 Gb/s PAM4斜坡采样CDR，具有同时四输出相位插值器（撤回Vol 166，art no 106872，2025）
errMICROELECTRONICS JOURNAL
IF2.3
err2025-12-01
err0
PREAI
errYang, Zekai; Zhao, Xiaoteng; Sun, Huajin; Su, Xianting; Dong, Zhicheng; Dong, Yilong; Yu, Yukui; Liang, Hongzhi; Liu, Shubin
err分享
err收藏
Offset-Immune Split-LSB Weight Calibration for Capacitor Mismatch and Gain Nonlinearity in Pipelined SAR ADC抗偏移分裂LSB权重校准方法用于流水线SAR ADC中的电容失配和增益非线性
errieee transactions on circuits and systems ii: express briefs
IF0
err2025-11-05
err0
PREAI
errLe Chen; Jinwei Zhang; Shubin Liu; Haolin Han
err分享
err收藏
A full-rate 8.2-to-15.1-Gb/s reference-less CDR using low-cost SAR-based frequency acquisition technique achieving 265ns acquisition time
errMICROELECTRONICS JOURNAL
IF2.3
err2025-11-01
err0
PREAI
errDong, Yilong; Zhao, Xiaoteng; Zhang, Yuhao; Chang, Hao; Qi, Yuxing; Yang, Zekai; Han, Chenxi; Liang, Hongzhi; Yu, Yukui; Liu, Shubin
err分享
err收藏
A Single-Channel 1–3 MASH SAR-Assisted Pipeline ADC With Residue Amplifier Error Shaping单通道1–3 MASH SAR辅助流水线ADC及其余量放大器误差整形
errIEEE Journal of Solid-State Circuits
IF5.6
err2025-09-25
err0
PREAI
errYanbo Zhang; Guolong Fu; Junyan Hao; Shubin Liu; Zhangming Zhu; Yan Zhu; Rui P. Martins; Chi-Hang Chan
err分享
err收藏
A 0.0006-mm2, 0.13-pJ/bit, 9–21-Gb/s Sub-Sampling CDR With Inverter-Based Frequency Multiplier and Embedded 1:3 DEMUX in 65-nm CMOS0.0006-mm2、0.13-pJ/bit、9–21-Gb/s亚采样CDR，采用基于反相器的频率倍增器和嵌入的1:3 DEMUX，在65-nm CMOS中实现
errIEEE Journal of Solid-State Circuits
IF5.6
err2025-09-05
err0
PREAI
errZhicheng Dong; Xiaoteng Zhao; Zekai Yang; Xianting Su; Haolin Han; Feng Bu; Depeng Sun; Shubin Liu; Zhangming Zhu
err分享
err收藏
A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator一种56 Gb/s PAM4斜率采样CDR，带有同时四输出相位插值器
errMICROELECTRONICS JOURNAL
IF2.3
err2025-09-01
err0
PREAI
errYang, Zekai; Zhao, Xiaoteng; Sun, Huajin; Su, Xianting; Dong, Zhicheng; Dong, Yilong; Yu, Yukui; Liang, Hongzhi; Liu, Shubin
err分享
err收藏
A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator一种56 Gb/s PAM4斜坡采样CDR，具有同时四输出相位插值器
errMICROELECTRONICS JOURNAL
IF2.3
err2025-09-01
err0
PREAI
errYang, Zekai; Zhao, Xiaoteng; Sun, Huajin; Su, Xianting; Dong, Zhicheng; Dong, Yilong; Yu, Yukui; Liang, Hongzhi; Liu, Shubin
err分享
err收藏
A 7-bit 8 GHz phase interpolator with eight-phase output using a linear weighting scheme using only 50 % interpolation units一种采用线性加权方案、仅使用50%插值单元的7位8 GHz八相输出相位插值器
errMICROELECTRONICS JOURNAL
IF2.3
err2025-09-01
err0
PREAI
errLiu, Jie; Su, Xianting; Yang, Zekai; Dong, Zhicheng; Han, Chenxi; Zhao, Xiaoteng; Liu, Shubin
err分享
err收藏
Load-driven inductive peaking design for broad band continuous-time linear equalizer负载驱动型电感峰化设计用于宽带连续时间线性均衡器
errMICROELECTRONICS JOURNAL
IF2.3
err2025-09-01
err0
PREAI
errZhang, Miao; Li, Ruidong; Zhao, Xiaoteng; Su, Xianting; Dong, Zhicheng; Yang, Zekai; Su, Hongyu; Liang, Hongzhi; Yu, Yukui; Liu, Shubin
err分享
err收藏
A design of 96 GS/s 7-bit DAC for high-speed wireline transmitter in 28-nm CMOS96 GS/s 7-bit DAC的高性能有线传输器设计（28-nm CMOS工艺）
errMICROELECTRONICS JOURNAL
IF2.3
err2025-09-01
err0
PREAI
errDeng, Junfei; Liu, Huolian; Han, Chenxi; Dang, Li; Liang, Hongzhi; Liu, Shubin
err分享
err收藏
A 5–18-GHz Reconfigurable Quadrature Receiver With Enhanced I–Q Isolation and 100–500-MHz Baseband Bandwidth一款5～18-GHz可重构正交接收机，具有增强的I-Q隔离和100～500-MHz基带带宽
errIEEE Journal of Solid-State Circuits
IF5.6
err2025-08-01
err0
PREAI
errJunyan Bi; Hao Xu; Tenghao Zou; Yaxin Zeng; Yechen Tian; Weitao He; Junjie Gu; Ziyang Jiao; Shubin Liu; Zhangming Zhu; Na Yan
err分享
err收藏
An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC With Dual-Path Time-Assisted Residue Generation Scheme一种固有PVT鲁棒的10位2.6-GS/s动态流水线ADC，采用双路径时间辅助余量生成方案
errIEEE Journal of Solid-State Circuits
IF5.6
err2025-07-01
err0
PREAI
errJunyan Hao; Minglei Zhang; Zijian Liu; Yanbo Zhang; Shubin Liu; Zhangming Zhu; Yan Zhu; Rui P. Martins; Chi-Hang Chan
err分享
err收藏
A Low-Noise Class-F23 VCO With Harmonic Resonance Expansion and 2nd/3rd-Harmonic Outputs for Multiband mm-Wave Applications一种低噪声Class-F23 VCO，采用谐波谐振扩展和2次/3次谐波输出，适用于多频段毫米波应用
errIEEE Transactions on Circuits and Systems I: Regular Papers
IF0
err2025-06-16
err0
PREAI
errYuan Gao; Depeng Sun; Chao Gu; Feng Bu; Bowen Wang; Rong Zhou; Zhicheng Dong; Xiaoteng Zhao; Tao Zhang; Ruixue Ding; Shubin Liu; Zhangming Zhu
err分享
err收藏

研究方向

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合作学者
合作期刊
J
J. Zhang
H 指数: 61 · 论文数: 168
R
Rui P. Martins
H 指数: 58 · 论文数: 1.1K
刘
刘杰 (Jie Liu)
H 指数: 51 · 论文数: 740
C
Changying Li
H 指数: 50 · 论文数: 260
孙
孙楠 (Nan Sun)
H 指数: 48 · 论文数: 303
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