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3D integration review
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DOI：10.1007/s11432-011-4226-7.png)
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Abstract
En 中文
3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.
Keywords:
3D integration
embedded memory
through silicon via
die stacking
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