.png){kind=icon}
返回
A 16-Core Processor With Shared-Memory and Message-Passing Communications
.png){kind=icon}
PRE
AI
DOI：10.1109/TCSI.2013.2283693.png)
.png){kind=icon}
原文求助.png){kind=icon}
分享.png){kind=icon}
收藏
摘要
En 中文
A 16-core processor with both message-passing and shared-memory inter-core communication mechanisms is implemented in 65 nm CMOS. Message-passing communication is enabled in a 3 6 Mesh packet-switched network-on-chip, and shared-memory communication is supported using the shared memory within each cluster. The processor occupies 9.1 mm(2) and operates fully functional at a clock rate of 750 MHz at 1.2 V and maximum 800 MHz at 1.3 V. Each core dissipates 34 mW under typical conditions at 750 MHz and 1.2 V while executing embedded applications such as an LDPC decoder, a 3780-point FFT module, an H. 264 decoder and an LTE channel estimator.
Keyword:
Chip multiprocessor
cluster-based
FFT
H.264 decoder
inter-core communication
inter-core synchronization
LDPC decoder
LTE channel estimator
message-passing
multi-core
network-on-chip
NoC
shared-memory
SIMD
期刊
IF:
5.2
论文数:
9.7K
被引数:
2.2W
机构
引用论文
.png){kind=icon}
Three‐Dimensional Graphene‐Based Nanomaterials as Electrocatalysts for Oxygen Reduction Reaction
OAAI
OAAI分享收藏
查看更多内容