返回
A Current-Based Write Method for Multibit IGZO 2T0C DRAM
DOI:10.1109/TED.2026.3669474.png)
摘要
En 中文
我们提出了一种在IGZO 2T0C DRAM中的新型基于电流的写入方法,用于补偿阈值电压(V-TH)变化。在写入操作期间,通过公共位线(BL)将电流写入2T0C单元,生成与不同电流值对应的自校准存储节点(SN)电压(V-SN)。被编程为相同电流值的单元在读取晶体管上产生相同的过驱动电压(V-SN-V-TH),从而实现与V-TH变化无关的高度均匀的读取电流。通过此设计,在25个IGZO 2T0C单元中实现了4位存储。这项工作为多比特DRAM应用开辟了一条新途径。
Keyword:
Random access memory
Transistors
Threshold voltage
Programming
Logic gates
Fabrication
Timing
Scanning electron microscopy
Fluctuations
Temperature
array
IGZO
multibit
VTH compensation
期刊
IF:
3.2
论文数:
790
被引数:
3.7W
机构
引用论文
EMBER: efficient multiple-bits-per-cell embedded RRAM macro for high-density digital storageEMBER:高效的多比特/单元嵌入式RRAM宏模块,用于高密度数字存储
First Demonstration of Monolithic Three-Dimensional Integration of Ultra-High Density Hybrid IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-Low Latency (<10ns), Record-Low Energy (<10fJ) of Data Transfer and Ultra-Long Data Retention (>5000s)首次演示单片三维集成超高密度混合IGZO/Si SRAM与IGZO 2T0C DRAM,实现记录级低延迟(<10ns)、记录级低能耗(<10fJ)的数据传输以及超长数据保持(>5000s)。
Impact of Oxide Thickness on Gate Capacitance—A Comprehensive Analysis on MOSFET, Nanowire FET, and CNTFET Devices氧化物厚度对栅电容的影响——MOSFET、纳米线FET和CNTFET器件的全面分析
Capacitor-less, Long-Retention (>400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM无电容器,长保留 (>400s) DRAM单元为低功耗和高密度单片3D DRAM铺平了道路

