A novel multiplexer-based low-power full adder

doi:10.1109/TCSII.2004.831429

A novel multiplexer-based low-power full adder

2004-07-01

98

PRE

AI

DOI：10.1109/TCSII.2004.831429

原文链接

原文求助

摘要

En 中文

The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF [1] and 10T [4]) and is 64% faster.

Keyword:

full adder

low power

multiplexer

very large-scale integrated (VLSI) circuit

A novel multiplexer-based low-power full adder

摘要

AI总结

期刊

机构

引用论文