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A scalable integration process for ultrafast two-dimensional flash memory

delete2024-08-12
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PRE
AI
蒋泳波 封面图
蒋泳波 (Yongbo Jiang)
C
Chunsen Liu
Z
Zhenyuan Cao
C
Chuhang Li
Z
Zizheng Liu
C
Chong Wang
Y
Yutong Xiang
周鹏 封面图
周鹏 (Peng Zhou) *
DOI:10.1038/s41928-024-01229-6delete
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摘要

摘要

En 中文
Data-driven computing is highly dependent on memory performance. Flash memory is presently the dominant non-volatile memory technology but suffers from limitations in terms of speed. Two-dimensional (2D) materials could potentially be used to create ultrafast flash memory. However, due to interface engineering problems, ultrafast non-volatile performance is presently restricted to exfoliated 2D materials, and there is a lack of performance demonstrations with short-channel devices. Here, we report a scalable integration process for ultrafast 2D flash memory that can be used to integrate 1,024 flash-memory devices with a yield of over 98%. We illustrate the approach with two different tunnelling barrier configurations of the memory stack (HfO2/Pt/HfO2 and Al2O3/Pt/Al2O3) and using transferred chemical vapour deposition-grown monolayer molybdenum disulfide. We also show that the channel length of the ultrafast flash memory can be scaled down to sub-10 nm, which is below the physical limit of silicon flash memory. Our sub-10 nm devices offer non-volatile information storage (up to 4 bits) and robust endurance (over 105). A scalable integration process for ultrafast two-dimensional flash memory can be used to integrate 1,024 devices with a yield of over 98%. The channel length of the devices could also be scaled down to sub-10 nm.
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期刊

Nature Electronics 封面图
Nature Electronics
IF:
40.9
论文数:
1.7K
被引数:
2.1W

机构

F
fudan university
学者数:
11.8W
论文数: 7.7W
被引数: 121
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