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AES S-Box Hardware With Efficiency Improvement Based on Linear Mapping Optimization
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DOI：10.1109/TCSII.2022.3185632.png)
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摘要
En 中文
This brief presents a new Advanced Encryption Standard (AES) S-Box hardware design based on linear mappings optimized by combining multiplicative and exponential offsets. Generally, the performance of S-Box with composite field representations depends on the structure of linear mappings (i.e., transformation matrices) between the polynomial field and composite field before and after the S-Box. So far, multiplicative and exponential offsets have been applied only to Boyar-Peralta type S-Box variants for optimizing the transformation matrix. In this brief, we apply the offset methods to another S-Box based on the redundant Galois field arithmetic and evaluate the performance by logic synthesis. Specifically, we design and evaluate two new types of S-Box hardware: one for encryption only (ENC) and the other for both encryption and decryption (ENC/DEC). The evaluation result confirms that the proposed ENC and ENC/DEC S-Boxes achieve a performance up to 8.7% and 28.8% higher, respectively, than the highest-performing conventional ones in terms of the area timing (AT) product.
Keyword:
Encryption
Hardware
Hamming weight
Minimization
Delays
Standards
Sparse matrices
AES
S-Box
hardware
linear mapping optimization
ASIC
期刊
I
IF:
4.9
论文数:
8.8K
被引数:
2.5W
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