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An algorithm for clock cycle selection in behavioral synthesis
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DOI：10.1016/S1383-7621(97)00020-9.png)
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摘要
En 中文
Most of the High Level Synthesis (HLS) tools proposed to date, carry out the synthesis process in clock cycles. This strategy may lead to implementations with a low clock cycle utilization. This problem becomes more important when multicycling is considered. In order to overcome it, we propose determining the clock cycle period during HLS. The technique is based on the minimization of the slack time of the operations thus allowing better clock period selection.
Keyword:
behavioral synthesis
clock estimation
clock selection
clock slack minimization
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