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E

Eugenio Villar

Universidad de Cantabria

21H指数
213论文数
1.5K被引数
收录论文 4
发表时间
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Automatic synthesis of communication and concurrency for exploring component-based system implementations considering UML channel semantics
errJOURNAL OF SYSTEMS ARCHITECTURE
IF4.1
err2015-09-01
err7
PREAI
errPosadas, Hector; Penil, Pablo; Nicolas, Alejandro; Villar, Eugenio
err分享
err收藏
The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems
errJOURNAL OF SYSTEMS ARCHITECTURE
IF4.1
err2014-01-01
err37
errOAAI
errHerrera, Fernando; Posadas, Hector; Penil, Pablo; Villar, Eugenio; Ferrero, Francisco; Valencia, Raul; Palermo, Gianluca
err分享
err收藏
An algorithm for clock cycle selection in behavioral synthesis
errJOURNAL OF SYSTEMS ARCHITECTURE
IF4.1
err1998-06-01
err0
PREAI
errTabuenca, P; Sanchez, P; Villar, E
err分享
err收藏
VHDL synthesis description portability: The need for level synthesis subsetsVHDL综合描述可移植性: 需要电平综合子集
errJOURNAL OF SYSTEMS ARCHITECTURE
IF4.1
err1996-09-01
err0
PREAI
errSelz, M; Ecker, W; Villar, E
err分享
err收藏

研究方向

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合作学者
合作期刊
G
Gianluca Palermo
H 指数: 30 · 论文数: 255
P
Pablo Peñil
H 指数: 27 · 论文数: 142
F
Francisco Ferrero
H 指数: 22 · 论文数: 143
W
Wolfgang Ecker
H 指数: 20 · 论文数: 205
H
Héctor Posadas
H 指数: 15 · 论文数: 62
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