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An Efficient Algorithm for Exact SRAM Verification via Novel Pattern-Matching Techniques
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DOI：10.1109/TCAD.2025.3602734.png)
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Abstract
En 中文
As semiconductor manufacturing advances into ultrascaled technology nodes, static random access memory (SRAM) verification faces critical challenges stemming from increasingly stringent geometries, heightened process variability, and the sheer density of contemporary designs. Existing methodologies, notably design rule checking (DRC) and conventional pattern matching, often fall short in capturing the intricate multilayer interactions and subtle geometric deviation characteristic of advanced SRAM layouts. These limitations can lead to missed layout anomalies and potential functional failures, resulting in diminished yield. This article introduces a specialized pattern-matching-based algorithm designed to address these challenges in SRAM verification. The algorithm integrates novel localization techniques, efficient spatial indexing, and an overlap detection procedure that together achieve exact verification while delivering substantial improvements in runtime performance. The experimental results confirm that this approach not only maintains 100% detection accuracy on complex SRAM benchmarks, but also achieves speedups ranging from threefold to over 20-fold compared to state-of-the-art methods, and from twofold to several thousandfold on classic single-layer pattern-matching datasets.
Keywords:
Pattern matching
Random access memory
Layout
Design automation
Arrays
Accuracy
Spatial indexes
Location awareness
Benchmark testing
Training
Design for manufacturability
overlap detection
pattern matching
spatial indexing
static random access memory (SRAM) verification
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