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An Efficient Layered Decoding Architecture for Nonbinary QC-LDPC Codes
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DOI：10.1109/TCSI.2011.2163889.png)
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Compared to binary low-density parity-check (LDPC) codes, nonbinary LDPC codes have better error performance when the code length is moderate. This paper presents an efficient layered decoder architecture for nonbinary quasi-cyclic (QC) LDPC codes using the proposed barrel-shifter-based permutation network and minimum value filter which is used to determine the first few smallest values from a given set. Through the permutation network, the decoding operations related to the multiplications over finite fields can be efficiently handled in the check-node operations, which simplifies the permutations in the variable-node operations and, hence, enables the layered decoder to be realized efficiently. In order to increase the throughput, we utilize the proposed permutation network and the minimum value filter to devise a selective-input min-max decoder architecture. Using a 90-nm CMOS process, we implemented three nonbinary decoders to demonstrate the proposed techniques.
Keyword:
Nonbinary low-density parity-check (LDPC) codes
min-max decoding algorithm
very large scale integration (VLSI) architecture
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5.2
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9.7K
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2.2W
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