Area- and Energy-Efficient LDPC Decoder Using Mixed-Resolution Check-Node Processing

doi:10.1109/TCSII.2021.3110953

Area- and Energy-Efficient LDPC Decoder Using Mixed-Resolution Check-Node Processing

2022-03-01

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DOI：10.1109/TCSII.2021.3110953

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A practical min-sum algorithm is associated with tree-based comparison units for the check-node operation, being a major bottleneck in designing low-cost and energy-efficient low-density parity-check (LDPC) decoders. In this brief, we present a cost-effective LDPC decoder architecture by changing its internal computing resolution for the power-hungry check-node processing. The proposed mixed-resolution comparison offers significant advantages in terms of both area and energy, while achieving error-correcting performance within 0.3 dB of the previous normalized min-sum (NMS) algorithm for a (1644, 1408) quasi-cyclic LDPC code of the 5G New Radio specifications. Compared to the baseline NMS architecture, the proposed decoder in a 65-nm CMOS technology reduces the hardware complexity and the power consumption by 28.4% and 23.1%, respectively, enhancing the area efficiency by more than 88.2%.

Keyword:

Decoding

Computer architecture

Complexity theory

Multiplexing

Hardware

Iterative decoding

Indexes

Error-correction code

LDPC decoding

cost-effective

energy-efficient

wireless communication

Area- and Energy-Efficient LDPC Decoder Using Mixed-Resolution Check-Node Processing

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