Conditional speculative mixed decimal/binary adders via binary-coded-chiliad encoding

doi:10.1016/j.compeleceng.2015.12.002

Conditional speculative mixed decimal/binary adders via binary-coded-chiliad encoding

2016-02-01

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DOI：10.1016/j.compeleceng.2015.12.002

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Decimal arithmetic circuits, based on IEEE-754-2008 standard, commonly use 10-bit densely-packed-decimal (DPD) encoding of three binary-coded-decimal (BCD) digits. Binary-coded-chiliad (BCC) encoding, as storage (arithmetic) efficient as DPD (BCD), equivalently packs three BCD digits. No unpacking/packing to/from BCD (entailing extra delay/power) per each arithmetic operation (required in case of DPD), are necessary for BCC. Therefore, while abiding to DPD standard, we are motivated to design decimal arithmetic operators that accept BCC operands and produce BCC results. As such, DPD data from memory or input devices are converted to BCC, manipulated in BCC and stored in the BCC register file, during multi-operation decimal computations, and converted back to DPD only on reporting results to memory or output devices. In this paper, following a previous simple mixed BCC/binary adder, we design and synthesize more efficient ones, and compare them with previous relevant BCD and BCC adders to show advantages in area, and power. (C) 2015 Elsevier Ltd. All rights reserved.

Keywords:

Decimal computer arithmetic

Speculative decimal addition

Mixed decimal/binary adder

Binary coded chiliad encoding

Densely packed decimal encoding

Conditional speculative mixed decimal/binary adders via binary-coded-chiliad encoding

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