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G

Ghassem Jaberipur

universidade de lisboa

17H指数
86论文数
1.2K被引数
收录论文 23
发表时间
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Design of energy-efficient and high-speed hybrid decimal adder能量高效与高速混合十进制加法器的设计
errJOURNAL OF SUPERCOMPUTING
IF2.7
err2025-02-11
err0
PREAI
errMashayekhi, Negin; Jaberipur, Ghassem; Reshadinezhad, Mohammad Reza; Moghimi, Shekoofeh
err分享
err收藏
Balanced Modular Addition for the Moduli Set {2q,2q∓1,22q+1} via Moduli-(2q∓√-1) Adders
errIEEE TRANSACTIONS ON COMPUTERS
IF3.8
err2025-01-01
err0
PREAI
errJaberipur, Ghassem; Rahman, Elham; Lee, Jeong-A
err分享
err收藏
RNPE: An MSDF and Redundant Number System-Based DNN Accelerator Engine
errIEEE ACCESS
IF3.6
err2024-01-01
err0
errOAAI
errMoghaddasi, Iraj; Jaberipur, Ghassem; Javaheri, Danial; Nam, Byeong-Gyu
err分享
err收藏
Sparse Matrix-Vector Multiplication Based on Online Arithmetic
errIEEE ACCESS
IF3.6
err2024-01-01
err1
errOAAI
errCherati, Sahar Moradi; Jaberipur, Ghassem; Sousa, Leonel
err分享
err收藏
A Parallel Prefix Modulo-(2q+2q-1+1) Adder via Diminished-1 Representation of Residues通过残基的减少-1表示的并行前缀模-(2q 2q-1 1) 加法器
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF4.9
err2023-08-01
err0
PREAI
errJaberipur, Ghassem; Badri, D.; Lee, Jeong-A
err分享
err收藏
Up to 8k-bit Modular Montgomery Multiplication in Residue Number Systems With Fast 16-bit Residue Channels具有快速16位残差通道的残差数系统中高达8k位模块化蒙哥马利乘法
errIEEE TRANSACTIONS ON COMPUTERS
IF3.8
err2021-01-01
err2
PREAI
errAhmadpour, Zabihollah; Jaberipur, Ghassem
err分享
err收藏
Majority-Logic, its applications, and atomic-scale embodiments
errCOMPUTERS & ELECTRICAL ENGINEERING
IF4.9
err2020-05-01
err15
errOAAI
errParhami, Behrooz; Abedi, Dariush; Jaberipur, Ghassem
err分享
err收藏
Fast division in the residue number system {2n+1,2n, 2n-1} based on shortcut mixed radix conversion
errCOMPUTERS & ELECTRICAL ENGINEERING
IF4.9
err2020-05-01
err7
PREAI
errTorabi, Zeinab; Jaberipur, Ghassem; Belghadr, Armin
err分享
err收藏
Balanced (3+2 log n)ΔG Adders for Moduli Set {2n+1, 2n+2n-1-1, 2n+1-1}
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF5.2
err2020-04-01
err2
PREAI
errJaberipur, Ghassem; Nadimi, Bardia
err分享
err收藏
Impact of diminished-1 encoding on residue number systems arithmetic units and converters减少-1编码对余数系统算术单元和转换器的影响
errCOMPUTERS & ELECTRICAL ENGINEERING
IF4.9
err2019-05-01
err4
PREAI
errJaberipur, Ghassem; Belghadr, Armin; Nejati, Saeed
err分享
err收藏
Adapting Computer Arithmetic Structures to Sustainable Supercomputing in Low-Power, Majority-Logic Nanotechnologies
errieee transactions on cloud computing
IF3.9
err2018-10-01
err12
PREAI
errJaberipur, Ghassem; Parhami, Behrooz; Abedi, Dariush
err分享
err收藏
FIR Filter Realization via Deferred End-Around Carry Modular Addition
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF5.2
err2018-09-01
err9
PREAI
errBelghadr, Armin; Jaberipur, Ghassem
err分享
err收藏
Decimal Full Adders Specially Designed for Quantum-Dot Cellular Automata专为量子点元胞自动机设计的十进制全加法器
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF4.9
err2018-01-01
err37
PREAI
errAbedi, Dariush; Jaberipur, Ghassem
err分享
err收藏
(5+2 inverted right perpendicular log n inverted left perpendicular)ΔG diminished-1 modulo-(2n+1) unified adder/subtractor with full zero handling(5 2倒右垂直对数n倒左垂直) Δ g减-1模-(2n 1) 带全零处理的统一加法器/减法器
errCOMPUTERS & ELECTRICAL ENGINEERING
IF4.9
err2017-07-01
err3
PREAI
errJaberipur, Ghassem; Belghadr, Armin
err分享
err收藏
Decimal Goldschmidt: A hardware algorithm for radix-10 division
errCOMPUTERS & ELECTRICAL ENGINEERING
IF4.9
err2016-07-01
err5
PREAI
errHosseiny, Adel; Jaberipur, Ghassem
err分享
err收藏
Conditional speculative mixed decimal/binary adders via binary-coded-chiliad encoding
errCOMPUTERS & ELECTRICAL ENGINEERING
IF4.9
err2016-02-01
err3
PREAI
errDorrigiv, M.; Jaberipur, G.
err分享
err收藏
(4+2log n)ΔG Parallel Prefix Modulo-(2n-3) Adder via Double Representation of Residues in [0,2](4 2log n)Δ g并行前缀模-(2n-3) 加法器通过 [0,2] 中残基的双重表示
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF4.9
err2015-06-01
err6
PREAI
errJaberipur, Ghassem; Langroudi, Seyed Hamed Fatemi
err分享
err收藏
Comment on High Speed Parallel Decimal Multiplication With Redundant Internal Encodings
errIEEE TRANSACTIONS ON COMPUTERS
IF3.8
err2015-01-01
err2
PREAI
errGorgin, Saeid; Jaberipur, Ghassem
err分享
err收藏
Improved CMOS (4;2) compressor designs for parallel multipliers
errCOMPUTERS & ELECTRICAL ENGINEERING
IF4.9
err2012-11-01
err31
PREAI
errPishvaie, Abdoreza; Jaberipur, Ghassem; Jahanian, Ali
err分享
err收藏
An improved maximally redundant signed digit adder
errCOMPUTERS & ELECTRICAL ENGINEERING
IF4.9
err2010-05-01
err10
PREAI
errJaberipur, Ghassem; Gorgin, Saeid
err分享
err收藏

研究方向

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合作学者
合作期刊
L
Leonel Sousa
H 指数: 39 · 论文数: 465
J
Jeong–A Lee
H 指数: 25 · 论文数: 234
M
Mohammad Ghodsi
H 指数: 21 · 论文数: 253
D
Danial Javaheri
H 指数: 17 · 论文数: 37
S
Saeid Gorgin
H 指数: 16 · 论文数: 96
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